Datasheet > GM71C4400CR-80

GM71C4400CR-80

更新时间： 2024-02-20 17:34:07

品牌	Logo	应用领域
乐金电子 - LG		内存集成电路光电二极管动态存储器
页数	文件大小	规格书
9页	107K
描述
1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM

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GM71C4400CR-80 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	TSOP, TSOP20/26,.36	Reach Compliance Code：	compliant
风险等级：	5.75	Is Samacsys：	N
最长访问时间：	80 ns	I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e0
内存密度：	4194304 bit	内存集成电路类型：	FAST PAGE DRAM
内存宽度：	4	端子数量：	20
字数：	1048576 words	字数代码：	1000000
最高工作温度：	70 °C	最低工作温度：
组织：	1MX4	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP
封装等效代码：	TSOP20/26,.36	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	电源：	5 V
认证状态：	Not Qualified	刷新周期：	1024
反向引出线：	YES	自我刷新：	NO
最大待机电流：	0.001 A	子类别：	DRAMs
最大压摆率：	0.09 mA	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

GM71C4400CR-80 数据手册

GM71C(S)4400C/CL

LG Semicon

10. tWCS, tRWD, tCWD tCPW and tAWD are not restrictive operating parameters. They are included in the

data sheet as electrical characteristics only; if tWCS >=tWCS(min), the cycle is an early write cycle

and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if

tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a read-

modify-write and the data output will contain data read from the selected cell; if neither of the

above sets of conditions is satisfied, the condition of the data out (at access time) is

indeterminate.

11. These parameters are referenced to CAS leading edge in early write cycles and to WE leading

edge in delayed write or a read modify write cycle.

12. tRASP defines RAS pulse width in fast page mode cycles.

13. Access time is determined by the longer of tAA or tCAC or tACP.

14. An initial pause of 100us is required after power up followed by a minimum of eight

initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal

refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required.

15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying

data to the device.

16. Test mode operation specified in this data sheet is 2-bit test function controlled by control

address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS

(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read

cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the

condition of the output data is low level. In order to end this test mode operation, perform a RAS

only refresh cycle or a CAS-before-RAS refresh cycle.

17. In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2ns to 5ns for

the specified value. These parameters should be specified in test mode cycles by adding the

above value to the specified value in this data sheet.

1...5 6 789

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与GM71C4400CR-80相关器件

型号	品牌	获取价格	描述	数据表
GM71C4400CT	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4400CT-60	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4400CT-60	HYNIX	获取价格	Fast Page DRAM, 1MX4, 60ns, CMOS, PDSO20,
GM71C4400CT-70	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4400CT-80	LG	获取价格	1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
GM71C4400CT-80	HYNIX	获取价格	Fast Page DRAM, 1MX4, 80ns, CMOS, PDSO20,
GM71C4400CZ-60	ETC	获取价格	x4 Fast Page Mode DRAM
GM71C4400CZ-70	HYNIX	获取价格	Fast Page DRAM, 1MX4, 70ns, CMOS, PZIP20
GM71C4400CZ-80	HYNIX	获取价格	Fast Page DRAM, 1MX4, 80ns, CMOS, PZIP20
GM71C4400D	LG	获取价格	1,048,576 Words x Bit Organization

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