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GM71C4400CR-80 PDF预览

GM71C4400CR-80

更新时间： 2024-09-19 22:07:11
品牌 Logo 应用领域
乐金电子 - LG 内存集成电路光电二极管动态存储器
页数 文件大小 规格书
9页 107K
描述
1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM

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中文翻译

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GM71C4400CR-80 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.75
Is Samacsys：N访问模式：FAST PAGE
最长访问时间：80 ns其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型：COMMONJESD-30 代码：R-PDSO-G20
JESD-609代码：e0内存密度：4194304 bit
内存集成电路类型：FAST PAGE DRAM内存宽度：4
功能数量：1端口数量：1
端子数量：20字数：1048576 words
字数代码：1000000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX4输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20/26,.36封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
刷新周期：1024反向引出线：YES
自我刷新：NO最大待机电流：0.001 A
子类别：DRAMs最大压摆率：0.09 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

GM71C4400CR-80 数据手册

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GM71C(S)4400C/CL  
LG Semicon  
10. tWCS, tRWD, tCWD tCPW and tAWD are not restrictive operating parameters. They are included in the  
data sheet as electrical characteristics only; if tWCS >=tWCS(min), the cycle is an early write cycle  
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if  
tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a read-  
modify-write and the data output will contain data read from the selected cell; if neither of the  
above sets of conditions is satisfied, the condition of the data out (at access time) is  
indeterminate.  
11. These parameters are referenced to CAS leading edge in early write cycles and to WE leading  
edge in delayed write or a read modify write cycle.  
12. tRASP defines RAS pulse width in fast page mode cycles.  
13. Access time is determined by the longer of tAA or tCAC or tACP.  
14. An initial pause of 100us is required after power up followed by a minimum of eight  
initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal  
refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required.  
15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying  
data to the device.  
16. Test mode operation specified in this data sheet is 2-bit test function controlled by control  
address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS  
(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read  
cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the  
condition of the output data is low level. In order to end this test mode operation, perform a RAS  
only refresh cycle or a CAS-before-RAS refresh cycle.  
17. In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2ns to 5ns for  
the specified value. These parameters should be specified in test mode cycles by adding the  
above value to the specified value in this data sheet.  
8
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GM71C4400CT-80 HYNIX

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GM71C4400CZ-60 ETC

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GM71C4400CZ-70 HYNIX

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GM71C4400D LG

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 		1,048,576 Words x Bit Organization

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