Datasheet > GAL20RA10B-30LP

GAL20RA10B-30LP

更新时间： 2024-09-19 22:51:03

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
15页	241K
描述
High-Speed Asynchronous E2CMOS PLD Generic Array Logic⑩

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

GAL20RA10B-30LP 数据手册

GAL20RA10

High-Speed Asynchronous E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 7.5 ns Maximum Propagation Delay

— Fmax = 83.3 MHz

— 9 ns Maximum from Clock Input to Data Output

OLMC

I/O/Q

— TTL Compatible 8 mA Outputs

— UltraMOS^®Advanced CMOS Technology

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

— 75mA Typical Icc

OLMC

• ACTIVE PULL-UPS ON ALL PINS

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100 ms)

— 20 Year Data Retention

I/O/Q

• TEN OUTPUT LOGIC MACROCELLS

— Independent Programmable Clocks

— Independent Asynchronous Reset and Preset

— Registered or Combinatorial with Polarity

— Full Function and Parametric Compatibility with

PAL20RA10

I/O/Q

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— State Machine Control

— Standard Logic Consolidation

— Multiple Clock Logic Designs

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description

The GAL20RA10 combines a high performance CMOS process

with electrically erasable (E²) floating gate technology to provide

the highest speed performance available in the PLD market. Lattice

Semiconductor’s E²CMOS circuitry achieves power levels as low

as 75mA typical I_CCwhich represents a substantial savings in power

when compared to bipolar counterparts. E²technology offers high

speed (<100ms) erase times providing the ability to reprogram,

reconfigure or test the devices quickly and efficiently.

Pin Configuration

DIP

Vcc

PLCC

I/O/Q

GAL

I/O/Q

20RA10

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. The GAL20RA10 is a direct parametric compatible CMOS

replacement for the PAL20RA10 device.

23 I/O/Q

GAL20RA10

Top View

I/O/Q

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacturing. Therefore, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

I/O/Q

GND

13 OE

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

July 1997

20ra10_02

12 3 4 5 6 7...15

中文翻译

下载PDF

与GAL20RA10B-30LP相关器件

型号	品牌	获取价格	描述	数据表
GAL20RA10B-7LJ	LATTICE	获取价格	High-Speed Asynchronous E2CMOS PLD Generic Ar
GAL20RA10B-7LJ	ROCHESTER	获取价格	EE PLD, 7.5 ns, PQCC28, PLASTIC, LCC-28
GAL20V8	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL20V8_06	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Log
GAL20V8-10LNC	ETC	获取价格	Electrically-Erasable PLD
GAL20V8-10LVC	ETC	获取价格	Electrically-Erasable PLD
GAL20V8-20LJC	TI	获取价格	EE PLD, 20ns, CDIP24, CERAMIC, DIP-24
GAL20V8-20LJI	TI	获取价格	EE PLD, 20ns, CDIP24, CERAMIC, DIP-24
GAL20V8-20LJM	ETC	获取价格	Electrically-Erasable PLD
GAL20V8-20LNI	TI	获取价格	EE PLD, 20ns, PDIP24, 0.300 INCH, SKINNY, PLASTIC, DIP-24

与GAL20RA10B-30LP相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

33
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

31
SL74HC10N：高性能三输入与非门解析
2024-09-03

103
AIC1781A 电池充电控制器深度解析
2024-09-03

98

产品中心

服务支持

精选活动

关于我们

帮助中心

GAL20RA10B-30LP

GAL20RA10B-30LP 数据手册

与GAL20RA10B-30LP相关器件

与GAL20RA10B-30LP相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GAL20RA10B-30LP

GAL20RA10B-30LP 数据手册

与GAL20RA10B-30LP相关器件

与GAL20RA10B-30LP相关文章

您还可以找

您在本页遇到什么问题？