Datasheet > GAL20V8_06

GAL20V8_06

更新时间： 2024-11-08 04:19:19

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
25页	578K
描述
High Performance E2CMOS PLD Generic Array Logic⑩

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中文翻译

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数据手册

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GAL20V8_06 数据手册

GAL20V8

High Performance E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 5 ns Maximum Propagation Delay

— Fmax = 166 MHz

I/CLK

IMUX

CLK

— 4 ns Maximum from Clock Input to Data Output

— UltraMOS^®Advanced CMOS Technology

I/O/Q

OLMC

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

— 75mA Typ Icc on Low Power Device

— 45mA Typ Icc on Quarter Power Device

I/O/Q

OLMC

• ACTIVE PULL-UPS ON ALL PINS

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Also Emulates 24-pin PAL^®Devices with Full Function/

Fuse Map/Parametric Compatibility

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

OLMC

IMUX

I/OE

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

• LEAD-FREE PACKAGE OPTIONS

Description

Pin Configuration

The GAL20V8C, at 5ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

able (E²) floating gate technology to provide the highest speed

performance available in the PLD market. High speed erase times

(<100ms) allow the devices to be reprogrammed quickly and ef-

ficiently.

DIP

PLCC

Vcc

I/CLK

I/O/Q

GAL

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. An important subset of the many architecture configura-

tions possible with the GAL20V8 are the PAL architectures listed

in the table of the macrocell description section. GAL20V8 devices

are capable of emulating any of these PAL architectures with full

function/fuse map/parametric compatibility.

20V8

25 I/O/Q

I/O/Q

GAL20V8

Top View

21 I/O/Q

I/O/Q

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

13 I/OE

GND

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2006

20v8_07

12 3 4 5 6 7...25

中文翻译

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与GAL20V8_06相关器件

型号	品牌	获取价格	描述	数据表
GAL20V8-10LNC	ETC	获取价格	Electrically-Erasable PLD
GAL20V8-10LVC	ETC	获取价格	Electrically-Erasable PLD
GAL20V8-20LJC	TI	获取价格	EE PLD, 20ns, CDIP24, CERAMIC, DIP-24
GAL20V8-20LJI	TI	获取价格	EE PLD, 20ns, CDIP24, CERAMIC, DIP-24
GAL20V8-20LJM	ETC	获取价格	Electrically-Erasable PLD
GAL20V8-20LNI	TI	获取价格	EE PLD, 20ns, PDIP24, 0.300 INCH, SKINNY, PLASTIC, DIP-24
GAL20V8-20LVI	ETC	获取价格	Electrically-Erasable PLD
GAL20V8-25LJC	ETC	获取价格	Electrically-Erasable PLD
GAL20V8-25LJI	TI	获取价格	EE PLD, 25ns, CDIP24, CERAMIC, DIP-24
GAL20V8-25LNI	ETC	获取价格	Electrically-Erasable PLD

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