Datasheet > GAL16VP8

GAL16VP8

更新时间： 2024-11-09 22:51:03

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
17页	214K
描述
High-Speed E2CMOS PLD Generic Array Logic

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GAL16VP8 数据手册

GAL16VP8

High-Speed E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

• HIGH DRIVE E²CMOS^®GAL^®DEVICE

— TTL Compatible 64 mA Output Drive

— 15 ns Maximum Propagation Delay

— Fmax = 80 MHz

I/CLK

CLK

— 10 ns Maximum from Clock Input to Data Output

I/O/Q

OLMC

— UltraMOS^®Advanced CMOS Technology

• ENHANCED INPUT AND OUTPUT FEATURES

— Schmitt Trigger Inputs

— Programmable Open-Drain or Totem-Pole Outputs

— Active Pull-Ups on All Inputs and I/O pins

• E²CELL TECHNOLOGY

— Reconfigurable Logic

I/O/Q

OLMC

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Architecturally Compatible with Standard GAL16V8

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— Ideal for Bus Control & Bus Arbitration Logic

— Bus Address Decode Logic

— Memory Address, Data and Control Circuits

— DMA Control

I/O/Q

I/OE

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description

The GAL16VP8, with 64 mA drive capability and 15 ns maximum

propagation delay time is ideal for Bus and Memory control appli-

Pin Configuration

cations.

The GAL16VP8 is manufactured using Lattice

DIP

Semiconductor's advanced E²CMOS process which combines

CMOS with Electrically Erasable (E²) floating gate technology. High

speed erase times (<100ms) allow the devices to be reprogrammed

quickly and efficiently.

PLCC

I/CLK

I/O/Q

I/CLK

I/O/Q

System bus and memory interfaces require control logic before

driving the bus or memory interface signals. The GAL16VP8

combines the familiar GAL16V8 architecture with bus drivers as

its outputs. The generic architecture provides maximum design flex-

ibility by allowing the Output Logic Macrocell (OLMC) to be con-

figured by the user. The 64mAoutput drive eliminates the need for

additional devices to provide bus driving capability.

GAL

I/O/Q

16VP8

I/O/Q

Vcc

GAL16VP8

Top View

GND

I/O/Q

GND

I/O/Q

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

I/OE I/O/Q I/O/Q I/O/Q

I/OE

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

December 1997

16vp8_03

12 3 4 5 6 7...17

中文翻译

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与GAL16VP8相关器件

型号	品牌	获取价格	描述	数据表
GAL16VP8B-15LJ	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL16VP8B-15LP	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL16VP8B-25LJ	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL16VP8B-25LP	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL16Z8-25LJC	TI	获取价格	EE PLD, 25ns, CDIP24, 0.300 INCH, CERAMIC, DIP-24
GAL16Z8-25LNC	TI	获取价格	EE PLD, 25ns, PDIP24, 0.300 INCH, PLASTIC, DIP-24
GAL18V10	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL18V10-15D	ETC	获取价格	ASIC
GAL18V10-15DI	ETC	获取价格	ASIC
GAL18V10-15DM	ETC	获取价格	ASIC

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