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GAL18V10-15LP PDF预览

GAL18V10-15LP

更新时间： 2024-09-19 22:25:11
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件光电二极管输入元件时钟
页数 文件大小 规格书
16页 267K
描述
High Performance E2CMOS PLD Generic Array Logic

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中文翻译

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GAL18V10-15LP 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：PLASTIC, DIP-20
针数：20Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.86其他特性：REGISTER PRELOAD; POWER-UP RESET
架构：PAL-TYPE最大时钟频率：50 MHz
JESD-30 代码：R-PDIP-T20JESD-609代码：e0
长度：26.125 mm专用输入次数：7
I/O 线路数量：10输入次数：18
输出次数：10产品条款数：96
端子数量：20最高工作温度：75 °C
最低工作温度：组织：7 DEDICATED INPUTS, 10 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：5 V可编程逻辑类型：EE PLD
传播延迟：15 ns认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Programmable Logic Devices
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL EXTENDED
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

GAL18V10-15LP 数据手册

 浏览型号GAL18V10-15LP的Datasheet PDF文件第2页浏览型号GAL18V10-15LP的Datasheet PDF文件第3页浏览型号GAL18V10-15LP的Datasheet PDF文件第4页浏览型号GAL18V10-15LP的Datasheet PDF文件第5页浏览型号GAL18V10-15LP的Datasheet PDF文件第6页浏览型号GAL18V10-15LP的Datasheet PDF文件第7页 
GAL18V10  
High Performance E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 7.5 ns Maximum Propagation Delay  
— Fmax = 111 MHz  
RESET  
I/CLK  
— 5.5 ns Maximum from Clock Input to Data Output  
8
— TTL Compatible 16 mA Outputs  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
I/O/Q  
I/O/Q  
— UltraMOS® Advanced CMOS Technology  
8
8
I
I
I
I
I
I
I
• LOW POWER CMOS  
— 75 mA Typical Icc  
• ACTIVE PULL-UPS ON ALL PINS  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
I/O/Q  
I/O/Q  
8
10  
10  
8
I/O/Q  
I/O/Q  
• TEN OUTPUT LOGIC MACROCELLS  
— Uses Standard 22V10 Macrocell Architecture  
— Maximum Flexibility for Complex Logic Designs  
• PRELOAD AND POWER-ON RESET OF REGISTERS  
— 100% Functional Testability  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
• APPLICATIONS INCLUDE:  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
8
8
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
8
Description  
PRESET  
The GAL18V10, at 7.5 ns maximum propagation delay time, com-  
bines a high performance CMOS process with Electrically Eras-  
able (E2) floating gate technology to provide a very flexible 20-pin  
PLD. CMOS circuitry allows the GAL18V10 to consume much less  
power when compared to its bipolar counterparts. The E2 technol-  
ogy offers high speed (<100ms) erase times, providing the ability  
to reprogram or reconfigure the device quickly and efficiently.  
Pin Configuration  
DIP  
PLCC  
1
20  
Vcc  
I/CLK  
By building on the popular 22V10 architecture, the GAL18V10  
eliminates the learning curve usually associated with using a new  
device architecture. The generic architecture provides maximum  
design flexibility by allowing the Output Logic Macrocell (OLMC)  
to be configured by the user. The GAL18V10 OLMC is fully com-  
patible with the OLMC in standard bipolar and CMOS 22V10 de-  
vices.  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I
I
I
I
I
I/CLK Vcc I/O/Q  
20  
2
GAL  
18  
I/O/Q  
I/O/Q  
4
6
I
18V10  
I
I
5
I
I
GAL18V10  
Top View  
16 I/O/Q  
I/O/Q  
15  
I
I
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
I
I
I/O/Q  
14  
8
9
11  
13  
I/O/Q GND I/O/Q I/O/Q I/O/Q  
I/O/Q  
GND  
10  
11  
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com  
July 1997  
1
18v10_03  
1234567...16

中文翻译

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GAL18V10-15LP 替代型号

型号 品牌 替代类型 描述 数据表
GAL18V10B-20LP LATTICE

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 High Performance E2CMOS PLD Generic Array Logic
GAL18V10B-15LP LATTICE

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 High Performance E2CMOS PLD Generic Array Logic
GAL18V10B-10LP LATTICE

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 High Performance E2CMOS PLD Generic Array Logic

与GAL18V10-15LP相关器件

型号 品牌 获取价格 描述 数据表
GAL18V10-15LPI LATTICE

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 		EE PLD, 15ns, PAL-Type, CMOS, PDIP20, SKINNY, PLASTIC, DIP-20
GAL18V10-15LPIB LATTICE

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 		EE PLD, 15ns, CMOS, PDIP20, SKINNY, PLASTIC, DIP-20
GAL18V10-15P ETC

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 		ASIC
GAL18V10-15PI ETC

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 		ASIC
GAL18V10-20D ETC

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 		ASIC
GAL18V10-20DI ETC

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 		ASIC
GAL18V10-20DM ETC

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 		ASIC
GAL18V10-20J ETC

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 		ASIC
GAL18V10-20JI ETC

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 		ASIC
GAL18V10-20LJ LATTICE

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 		High Performance E2CMOS PLD Generic Array Logic

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