Datasheet > 可编程逻辑 > 可编程逻辑器件> GAL18V10-20LJ

GAL18V10-20LJ

更新时间： 2024-11-07 22:25:11

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
16页	267K
描述
High Performance E2CMOS PLD Generic Array Logic

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中文翻译

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数据手册

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GAL18V10-20LJ 数据手册

GAL18V10

High Performance E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 7.5 ns Maximum Propagation Delay

— Fmax = 111 MHz

RESET

I/CLK

— 5.5 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Outputs

OLMC

I/O/Q

— UltraMOS^®Advanced CMOS Technology

• LOW POWER CMOS

— 75 mA Typical Icc

• ACTIVE PULL-UPS ON ALL PINS

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

I/O/Q

• TEN OUTPUT LOGIC MACROCELLS

— Uses Standard 22V10 Macrocell Architecture

— Maximum Flexibility for Complex Logic Designs

• PRELOAD AND POWER-ON RESET OF REGISTERS

— 100% Functional Testability

I/O/Q

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description

PRESET

The GAL18V10, at 7.5 ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

able (E²) floating gate technology to provide a very flexible 20-pin

PLD. CMOS circuitry allows the GAL18V10 to consume much less

power when compared to its bipolar counterparts. The E²technol-

ogy offers high speed (<100ms) erase times, providing the ability

to reprogram or reconfigure the device quickly and efficiently.

Pin Configuration

DIP

PLCC

Vcc

I/CLK

By building on the popular 22V10 architecture, the GAL18V10

eliminates the learning curve usually associated with using a new

device architecture. The generic architecture provides maximum

design flexibility by allowing the Output Logic Macrocell (OLMC)

to be configured by the user. The GAL18V10 OLMC is fully com-

patible with the OLMC in standard bipolar and CMOS 22V10 de-

vices.

I/O/Q

I/CLK Vcc I/O/Q

GAL

I/O/Q

18V10

GAL18V10

Top View

16 I/O/Q

I/O/Q

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

I/O/Q

I/O/Q GND I/O/Q I/O/Q I/O/Q

I/O/Q

GND

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

July 1997

18v10_03

12 3 4 5 6 7...16

中文翻译

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与GAL18V10-20LJ相关器件

型号	品牌	获取价格	描述	数据表
GAL18V10-20LJB	LATTICE	获取价格	EE PLD, 20ns, PAL-Type, CMOS, PQCC20, PLASTIC, LCC-20
GAL18V10-20LJI	ETC	获取价格	Electrically-Erasable PLD
GAL18V10-20LJIB	LATTICE	获取价格	EE PLD, 20ns, CMOS, PQCC20, PLASTIC, LCC-20
GAL18V10-20LP	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL18V10-20LPB	LATTICE	获取价格	EE PLD, 20ns, PAL-Type, CMOS, PDIP20, SKINNY, PLASTIC, DIP-20
GAL18V10-20LPI	ETC	获取价格	Electrically-Erasable PLD
GAL18V10-20LPIB	LATTICE	获取价格	EE PLD, 20ns, CMOS, PDIP20, SKINNY, PLASTIC, DIP-20
GAL18V10-20P	ETC	获取价格	ASIC
GAL18V10-20PI	ETC	获取价格	ASIC
GAL18V10B-10LJ	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic

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