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FIN1028_04

更新时间: 2024-10-27 03:36:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
10页 1040K
描述
3.3V LVDS 2-Bit High Speed Differential Receiver

FIN1028_04 数据手册

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March 2001  
Revised May 2004  
FIN1028  
3.3V LVDS 2-Bit High Speed Differential Receiver  
General Description  
Features  
This dual receiver is designed for high speed interconnects  
utilizing Low Voltage Differential Signaling (LVDS) technol-  
ogy. The receiver translates LVDS levels, with a typical dif-  
ferential input threshold of 100 mV, to LVTTL signal levels.  
LVDS provides low EMI at ultra low power dissipation even  
at high frequencies. This device is ideal for high speed  
transfer of clock and data.  
Greater than 400Mbs data rate  
3.3V power supply operation  
0.4ns maximum differential pulse skew  
2.5ns maximum propagation delay  
Low power dissipation  
Power-Off protection  
The FIN1028 can be paired with its companion driver, the  
FIN1027, or any other LVDS driver.  
Fail safe protection for open-circuit, shorted and  
terminated conditions  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Flow-through pinout simplifies PCB layout  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1028M  
(Note 1)  
M08A  
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
FIN1028K8X  
(Preliminary)  
MAB08A  
MLP08C  
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide  
[TAPE and REEL]  
FIN1028MPX  
(Preliminary)  
8-Terminal Molded Leadless Package (MLP) Dual, MO-229, 2mm Square  
[TAPE and REEL]  
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pin Descriptions  
Connection Diagrams  
Pin Name  
Description  
LVTTL Data Outputs  
Non-inverting LVDS Inputs  
Inverting LVDS Inputs  
Power Supply  
Pin Assignment for SOIC  
R
OUT1, ROUT2  
RIN1+, RIN2+  
RIN1, RIN2−  
VCC  
GND  
Ground  
Function Table  
Input  
RIN+  
Outputs  
RIN+  
ROUT  
(Top View)  
L
H
L
L
H
H
Terminal Assignments for MLP  
H
Fail Safe Condition  
H = HIGH Logic Level  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
(Top Through View)  
© 2004 Fairchild Semiconductor Corporation  
DS500503  
www.fairchildsemi.com  

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