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FIN1028M PDF预览

FIN1028M

更新时间: 2024-10-26 22:49:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
9页 1030K
描述
3.3V LVDS 2-Bit High Speed Differential Receiver

FIN1028M 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.46
Is Samacsys:N输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:EIA-644; TIA-644
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.902 mm湿度敏感等级:1
功能数量:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
最大输出低电流:0.008 A封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:2.5 ns
接收器位数:2座面最大高度:1.75 mm
子类别:Line Driver or Receivers最大压摆率:9 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

FIN1028M 数据手册

 浏览型号FIN1028M的Datasheet PDF文件第2页浏览型号FIN1028M的Datasheet PDF文件第3页浏览型号FIN1028M的Datasheet PDF文件第4页浏览型号FIN1028M的Datasheet PDF文件第5页浏览型号FIN1028M的Datasheet PDF文件第6页浏览型号FIN1028M的Datasheet PDF文件第7页 
March 2001  
Revised June 2003  
FIN1028  
3.3V LVDS 2-Bit High Speed Differential Receiver  
General Description  
Features  
This dual receiver is designed for high speed interconnects  
utilizing Low Voltage Differential Signaling (LVDS) technol-  
ogy. The receiver translates LVDS levels, with a typical dif-  
ferential input threshold of 100 mV, to LVTTL signal levels.  
LVDS provides low EMI at ultra low power dissipation even  
at high frequencies. This device is ideal for high speed  
transfer of clock and data.  
Greater than 400Mbs data rate  
3.3V power supply operation  
0.4ns maximum differential pulse skew  
2.5ns maximum propagation delay  
Low power dissipation  
Power-Off protection  
The FIN1028 can be paired with its companion driver, the  
FIN1027, or any other LVDS driver.  
Fail safe protection for open-circuit, shorted and  
terminated conditions  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Flow-through pinout simplifies PCB layout  
8-Lead SOIC and 8-terminal MLP packages save space  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1028M  
(Note 1)  
M08A  
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
FIN1028MPX  
(Preliminary)  
MLP08C  
8-Terminal Molded Leadless Package (MLP) Dual, JEDEC MO-229, 2mm Square  
[TAPE and REEL]  
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pin Descriptions  
Connection Diagrams  
Pin Name  
ROUT1, ROUT2  
RIN1+, RIN2+  
RIN1, RIN2−  
VCC  
Description  
LVTTL Data Outputs  
Non-inverting LVDS Inputs  
Inverting LVDS Inputs  
Power Supply  
Pin Assignment for SOIC  
GND  
Ground  
Function Table  
Input  
Outputs  
RIN+  
RIN+  
ROUT  
L
H
L
L
H
H
(Top View)  
H
Fail Safe Condition  
Terminal Assignments for MLP  
H = HIGH Logic Level  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
(Top Through View)  
© 2003 Fairchild Semiconductor Corporation  
DS500503  
www.fairchildsemi.com  

FIN1028M 替代型号

型号 品牌 替代类型 描述 数据表
FIN1028MX FAIRCHILD

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Line Receiver, 2 Func, 2 Rcvr, CMOS, PDSO8, 0.150 INCH, MS-012, SOIC-8

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