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FIN1028MPX PDF预览

FIN1028MPX

更新时间: 2024-10-26 22:24:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
9页 1030K
描述
3.3V LVDS 2-Bit High Speed Differential Receiver

FIN1028MPX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SON包装说明:HVSON, SOLCC8,.08,20
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.79输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:EIA-644; TIA-644
JESD-30 代码:S-XDSO-N8JESD-609代码:e0
长度:2 mm功能数量:2
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C最大输出低电流:0.008 A
封装主体材料:UNSPECIFIED封装代码:HVSON
封装等效代码:SOLCC8,.08,20封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
最大接收延迟:2.5 ns接收器位数:2
座面最大高度:1 mm子类别:Line Driver or Receivers
最大压摆率:9 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:2 mmBase Number Matches:1

FIN1028MPX 数据手册

 浏览型号FIN1028MPX的Datasheet PDF文件第2页浏览型号FIN1028MPX的Datasheet PDF文件第3页浏览型号FIN1028MPX的Datasheet PDF文件第4页浏览型号FIN1028MPX的Datasheet PDF文件第5页浏览型号FIN1028MPX的Datasheet PDF文件第6页浏览型号FIN1028MPX的Datasheet PDF文件第7页 
March 2001  
Revised June 2003  
FIN1028  
3.3V LVDS 2-Bit High Speed Differential Receiver  
General Description  
Features  
This dual receiver is designed for high speed interconnects  
utilizing Low Voltage Differential Signaling (LVDS) technol-  
ogy. The receiver translates LVDS levels, with a typical dif-  
ferential input threshold of 100 mV, to LVTTL signal levels.  
LVDS provides low EMI at ultra low power dissipation even  
at high frequencies. This device is ideal for high speed  
transfer of clock and data.  
Greater than 400Mbs data rate  
3.3V power supply operation  
0.4ns maximum differential pulse skew  
2.5ns maximum propagation delay  
Low power dissipation  
Power-Off protection  
The FIN1028 can be paired with its companion driver, the  
FIN1027, or any other LVDS driver.  
Fail safe protection for open-circuit, shorted and  
terminated conditions  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Flow-through pinout simplifies PCB layout  
8-Lead SOIC and 8-terminal MLP packages save space  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1028M  
(Note 1)  
M08A  
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
FIN1028MPX  
(Preliminary)  
MLP08C  
8-Terminal Molded Leadless Package (MLP) Dual, JEDEC MO-229, 2mm Square  
[TAPE and REEL]  
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pin Descriptions  
Connection Diagrams  
Pin Name  
ROUT1, ROUT2  
RIN1+, RIN2+  
RIN1, RIN2−  
VCC  
Description  
LVTTL Data Outputs  
Non-inverting LVDS Inputs  
Inverting LVDS Inputs  
Power Supply  
Pin Assignment for SOIC  
GND  
Ground  
Function Table  
Input  
Outputs  
RIN+  
RIN+  
ROUT  
L
H
L
L
H
H
(Top View)  
H
Fail Safe Condition  
Terminal Assignments for MLP  
H = HIGH Logic Level  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
(Top Through View)  
© 2003 Fairchild Semiconductor Corporation  
DS500503  
www.fairchildsemi.com  

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