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FIN1032 PDF预览

FIN1032

更新时间: 2024-10-26 22:49:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
6页 249K
描述
3.3V LVDS 4-Bit High Speed Differential Receiver

FIN1032 数据手册

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August 2001  
Revised December 2001  
FIN1032  
3.3V LVDS 4-Bit High Speed Differential Receiver  
General Description  
Features  
This quad receiver is designed for high speed interconnect  
utilizing Low Voltage Differential Signaling (LVDS) technol-  
ogy. The receiver translates LVDS levels, with a typical dif-  
ferential input threshold of 100mV, to LVTTL signal levels.  
LVDS provides low EMI at ultra low power dissipation even  
at high frequencies. This device is ideal for high speed  
transfer of clock and data.  
Greater than 400Mbs data rate  
3.3V power supply operation  
0.4ns maximum differential pulse skew  
2.5ns maximum propagation delay  
Low power dissipation  
Power OFF protection  
The FIN1032 can be paired with its companion driver, the  
FIN1031, or any other Fairchild LVDS driver.  
Fail safe protection for open-circuit, shorted and termi-  
nated conditions  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Pin compatible with equivalent RS-422 and LVPECL  
devices  
16-Lead SOIC and TSSOP packages save space  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1032M  
M16A  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
FIN1032MTC  
MTC16  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Function Table  
Connection Diagram  
Inputs  
Outputs  
ROUT  
RIN+  
ROUT−  
EN  
H
H
H
X
EN  
X
X
X
L
H
L
L
H
L
H
Fail Safe Condition  
H
H
L
H
L
L
X
L
H
X
L
Fail Safe Condition  
X
H
Z
L
H
H = HIGH Logic Level  
Z = High Impedance  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
X = Don’t Care  
Pin Descriptions  
Pin Name  
OUT1, ROUT2, ROUT3, ROUT4  
RIN1+, RIN2+, RIN3+, RIN4+  
RIN1, RIN2, RIN3, RIN4−  
EN  
Description  
LVTTL Data Outputs  
Non-Inverting LVDS Inputs  
Inverting LVDS Inputs  
Driver Enable Pin  
R
EN  
VCC  
GND  
Inverting Driver Enable Pin  
Power Supply  
Ground  
© 2001 Fairchild Semiconductor Corporation  
DS500508  
www.fairchildsemi.com  

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