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FDC6506 PDF预览

FDC6506

更新时间: 2024-09-29 22:49:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
8页 205K
描述
Dual P-Channel Logic Level PowerTrench⑩ MOSFET

FDC6506 数据手册

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February 1999  
FDC6506P  
Dual P-Channel Logic Level PowerTrench MOSFET  
Features  
General Description  
These P-Channel logic level MOSFETs are produced using  
Fairchild Semiconductor's advanced PowerTrench  
process that has been especially tailored to minimize  
on-state resistance and yet maintain low gate charge for  
superior switching performance.  
-1.8 A, -30 V. RDS(on) = 0.170 @ VGS = -10 V  
RDS(on) = 0.280 @ VGS = -4.5 V  
Low gate charge (2.3nC typical).  
Fast switching speed.  
These devices have been designed to offer exceptional  
power dissipation in a very small footprint for applications  
where the bigger more expensive SO-8 and TSSOP-8  
packages are impractical.  
High performance trench technology for extremely  
low RDS(ON)  
.
SuperSOTTM-6 package: small footprint (72% smaller  
than standard SO-8); low profile (1mm thick).  
Applications  
Load switch  
Battery protection  
Power management  
D2  
S1  
3
2
1
4
5
6
D1  
G2  
S2  
SuperSOT TM-6  
G1  
TA = 25°C unless otherwise noted  
Absolute Maximum Ratings  
Symbol  
Parameter  
Ratings  
Units  
VDSS  
VGSS  
ID  
Drain-Source Voltage  
Gate-Source Voltage  
-30  
V
V
A
20  
±
(Note 1a)  
Drain Current - Continuous  
- Pulsed  
-1.8  
-10  
(Note 1a)  
(Note 1b)  
PD  
Power Dissipation for Single Operation  
0.96  
0.9  
W
(Note 1c)  
0.7  
TJ, Tstg  
Operating and Storage Junction Temperature Range  
-55 to +150  
C
°
Thermal Characteristics  
θ
(Note 1a)  
(Note 1)  
R
R
Thermal Resistance, Junction-to-Ambient  
Thermal Resistance, Junction-to-Case  
130  
60  
C/W  
C/W  
JA  
°
°
JC  
θ
Package Outlines and Ordering Information  
Device Marking  
506  
Device  
Reel Size  
Tape Width  
Quantity  
3000 units  
FDC6506P  
7’’  
8mm  
.
1999 Fairchild Semiconductor Corporation  
FDC6506P Rev. C  

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