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EVAL-AD9834EB PDF预览

EVAL-AD9834EB

更新时间: 2024-11-23 22:49:07
品牌 Logo 应用领域
亚德诺 - ADI 数据分配系统
页数 文件大小 规格书
20页 232K
描述
Low Power, +2.3 V to +5.5 V, 50 MHz Complete DDS

EVAL-AD9834EB 数据手册

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PRELIMINARY TECHNICAL DATA  
Low Power, +2.3 V to +5.5 V, 50 MHz  
a
PreliminaryTechnicalData  
CompleteDDS  
AD9834  
Capability for phase modulation and frequency modula-  
tion is provided. Frequency accuracy can be controlled to  
one part in 0.25 billion. Modulation is effected by loading  
registers through the serial interface.  
FEATURES  
+2.3 V to +5.5 V Power Supply  
50 MHz Speed  
Low Jitter Clock Output  
Sine Output/Triangular Output  
Serial Loading  
Power-Down Option  
Narrowband SFDR > 72 dB  
20 mW Power Consumption at 3 V  
20-Pin TSSOP  
The AD9834 offers the user a variety of output  
waveforms. The SIN ROM can be bypassed so that a  
linear up/down ramp is output from the DAC. If the SIN  
ROM is not by-passed, a sinusoidal output is available.  
Also, if a clock output is required, the MSB of the DAC  
data can be output, or the on-chip comparator can be  
used.  
APPLICATIONS  
Test Equipment  
Slow Sweep Generator  
DDS Tuning  
The digital section is driven by an on-board regulator  
which steps down the applied DVDD to +2.5 V when  
DVDD exceeds +2.5 V. The analog and digital sections  
are independent and can be run from different power  
supplies e.g. AVDD can equals 5 V with DVDD equal to  
3 V, etc.  
Digital Modulation  
GENERAL DESCRIPTION  
The AD9834 is a numerically controlled oscillator  
employing a phase accumulator, a SIN ROM and a  
10-bit D/A converter integrated on a single CMOS  
chip. Clock rates up to 50 MHz are supported with a  
power supply from 2.3 V to 5.5 V.  
The AD9834 has a power-down pin (SLEEP) which  
allows external control of a power-down mode. Sections of  
the device which are not being used can be powered down to  
minimise the current consumption e.g. the DAC can be  
powered down when a clock output is being generated.  
The part is available in a 20-pin TSSOP package.  
FUNCTIONAL BLOCK DIAGRAM  
AVDD AGND  
DGND  
DVDD  
CAP/2.5V  
REFOUT  
FS ADJUST  
On-Board  
Reference  
MCLK  
Regulator  
FullScale  
Control  
COMP  
VCC  
2.5V  
FSELECT  
28 Bit  
FREQ0 REG  
IOUT  
Phase  
Accumulator  
(28 Bit)  
12  
10-Bit  
DAC  
SIN  
ROM  
MUX  
MUX  
IOUTB  
28 Bit  
FREQ1 REG  
MSB  
MUX  
DIV BY  
2
12 Bit PHASE0 REG  
MUX  
12 Bit PHASE1 REG  
MUX  
SIGN BIT OUT  
VIN  
16 Bit Control  
Register  
COMPARATOR  
Serial Interface  
&
Control Logic  
AD9834  
FSYNC SCLK  
SDATA  
PSELECT  
SLEEP  
RESET  
REV PrM 04/02  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2002  

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