Low Power, 8.5 mW, 2.3 V to 5.5 V,
Programmable Waveform Generator
AD9837
FEATURES
GENERAL DESCRIPTION
Digitally programmable frequency and phase
8.5 mW power consumption at 2.3 V
MCLK speed: 16 MHz (B grade), 5 MHz (A grade)
28-bit resolution: 0.06 Hz at 16 MHz reference clock
Sinusoidal, triangular, and square wave outputs
2.3 V to 5.5 V power supply
3-wire SPI interface
Extended temperature range: −40°C to +125°C
Power-down option
The AD9837 is a low power, programmable waveform generator
capable of producing sine, triangular, and square wave outputs.
Waveform generation is required in various types of sensing,
actuation, and time domain reflectometry (TDR) applications.
The output frequency and phase are software programmable,
allowing easy tuning. The frequency registers are 28 bits wide:
with a 16 MHz clock rate, resolution of 0.06 Hz can be achieved;
with a 5 MHz clock rate, the AD9837 can be tuned to 0.02 Hz
resolution.
10-lead LFCSP
The AD9837 is written to via a 3-wire serial interface. This serial
interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards. The device operates
with a power supply from 2.3 V to 5.5 V.
APPLICATIONS
Frequency stimulus/waveform generation
Liquid and gas flow measurement
Sensory applications: proximity, motion,
and defect detection
Line loss/attenuation
Test and medical equipment
The AD9837 has a power-down (sleep) function. Sections of the
device that are not being used can be powered down to minimize
the current consumption of the part. For example, the DAC can
be powered down when a clock output is being generated.
Sweep/clock generators
Time domain reflectometry (TDR) applications
The AD9837 is available in a 10-lead LFCSP_WD package.
FUNCTIONAL BLOCK DIAGRAM
AGND
DGND
VDD
CAP/2.5V
ON-BOARD
REFERENCE
REGULATOR
2.5V
MCLK
AVDD/
DVDD
FULL-SCALE
CONTROL
COMP
28-BIT FREQ0 REG
28-BIT FREQ1 REG
12
PHASE
ACCUMULATOR
(28-BIT)
SIN
ROM
10-BIT DAC
MUX
MUX
MSB
12-BIT PHASE0 REG
12-BIT PHASE1 REG
MUX
DIVIDE
BY 2
VOUT
MUX
16-BIT CONTROL REGISTER
R
200Ω
SERIAL INTERFACE
AND
CONTROL LOGIC
AD9837
FSYNC
SCLK
SDATA
Figure 1.
Rev. 0
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