Datasheet > EVAL-ADAU1979Z

EVAL-ADAU1979Z

更新时间： 2024-11-24 12:36:35

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
44页	1698K
描述
Quad Analog-to-Digital Converter (ADC)

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EVAL-ADAU1979Z 数据手册

Quad Analog-to-Digital Converter (ADC)

Data Sheet

ADAU1979

FEATURES

GENERAL DESCRIPTION

Four 4.5 V rms (typical) differential inputs

On-chip phase-locked loop (PLL) for master clock

Low electromagnetic interference (EMI) design

109 dB (typical) analog-to-digital converter (ADC) dynamic

range

Total harmonic distortion + noise (THD + N): −95 dB (typical)

Selectable digital high-pass filter

24-bit stereo ADC with 8 kHz to 192 kHz sample rates

Digital volume control with autoramp function

I²C/SPI controllable for flexibility

Software-controllable clickless mute

Software power-down

Right justified, left justified, I²S, and TDM modes

Master and slave operation modes

40-lead LFCSP package

The ADAU1979 incorporates four high performance, analog-to-

digital converters (ADCs) with 4.5 V rms capable ac-coupled

inputs. The ADCs use a multibit sigma-delta (Σ-Δ) architecture

with continuous time front end for low EMI. An I²C/serial

peripheral interface (SPI) control port is included that allows a

microcontroller to adjust volume and many other parameters.

The ADAU1979 uses only a single 3.3 V supply. The device

internally generates the required digital DVDD supply. The low

power architecture reduces the power consumption. The on-

chip PLL can derive the master clock from an external clock

input or frame clock (sample rate clock). When fed with the

frame clock, it eliminates the need for a separate high frequency

master clock in the system. The ADAU1979 is available in a

40-lead LFCSP package.

Note that throughout this data sheet, multifunction pins, such

as SCL/CCLK, are referred to either by the entire pin name or

by a single function of the pin, for example, CCLK, when only

that function is relevant.

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Active noise cancellation systems

FUNCTIONAL BLOCK DIAGRAM

3.3V TO 1.8V

REGULATOR

DVDD

ADAU1979

AVDDx

AIN1

AIN2

AIN3

AIN4

IOVDD

ADC

LRCLK

BCLK

ADC

SDATAOUT1

SDATAOUT2

AGNDx

SCL/CCLK

SDA/COUT

AVDDx

ADDR1/CIN

ADDR0/CLATCH

I C/SPI

REF

CONTROL

PLL

PD/RST

AGNDx

Figure 1.

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

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