Datasheet > EVAL-ADAU1446EBZ

EVAL-ADAU1446EBZ

更新时间： 2024-11-27 12:53:55

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
92页	1008K
描述
SigmaDSP Digital Audio Processor

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中文翻译

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数据手册

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EVAL-ADAU1446EBZ 数据手册

SigmaDSP Digital Audio Processor

with Flexible Audio Routing Matrix

ADAU1442/ADAU1445/ADAU1446

I²C and SPI control interfaces

FEATURES

Standalone operation

Self-boot from serial EEPROM

Fully programmable audio digital signal processor (DSP) for

enhanced sound processing

4-channel, 10-bit auxiliary control ADC

Multipurpose pins for digital controls and outputs

Easy implementation of available third-party algorithms

On-chip regulator for generating 1.8 V from 3.3 V supply

100-lead TQFP and LQFP packages

Features SigmaStudio, a proprietary graphical programming

tool for the development of custom signal flows

172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz

4k parameter RAM, 8k data RAM

Flexible audio routing matrix (FARM)

24-channel digital input and output

Temperature range: −40°C to +105°C

Up to 8 stereo asynchronous sample rate converters

(from 1:8 up to 7.75:1 ratio and 139 dB DNR)

Stereo S/PDIF input and output

Supports serial and TDM I/O, up to f_S= 192 kHz

Multichannel byte-addressable TDM serial port

Pool of 170 ms digital audio delay (at 48 kHz)

Clock oscillator for generating master clock from crystal

PLL for generating core clock from common audio clocks

APPLICATIONS

Automotive audio processing

Head units

Navigation systems

Rear-seat entertainment systems

DSP amplifiers (sound system amplifiers)

Commercial audio processing

FUNCTIONAL BLOCK DIAGRAM

MP[3:0]/

SPI/I C* SELFBOOT MP[11:4] ADC[3:0]

XTALI XTALO

ADAU1442/

ADAU1445/

ADAU1446

I C/SPI CONTROL

INTERFACE

MP/

AUX ADC

CLOCK

OSCILLATOR

CLKOUT

PLL

AND SELF-BOOT

1.8V

REGULATOR

PROGRAMMABLE AUDIO

PROCESSOR CORE

S/PDIF

RECEIVER

S/PDIF

TRANSMITTER

SPDIFI

SPDIFO

FLEXIBLE AUDIO ROUTING MATRIX

(FARM)

SDATA_IN[8:0]

(24-CHANNEL

DIGITAL AUDIO

INPUT)

SDATA_OUT[8:0]

(24-CHANNEL

DIGITAL AUDIO

OUTPUT)

SERIAL DATA

INPUT PORT

SERIAL DATA

OUTPUT PORT

(×9)

UP TO 16 CHANNELS OF

ASYNCHRONOUS

SAMPLE RATE

(×9)

CONVERTERS

†

BIT CLOCK

(BCLK)

SERIAL CLOCK

DOMAINS

†

(×12)

FRAME CLOCK

(LRCLK)

FRAME CLOCK

(LRCLK)

*SPI/I C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS.

†

THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS,

SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS.

Figure 1.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

12 3 4 5 6 7...92

中文翻译

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与EVAL-ADAU1446EBZ相关器件

型号	品牌	获取价格	描述	数据表
EVAL-ADAU1452MINIZ	ADI	获取价格	SigmaDSP Digital Audio Processor
EVAL-ADAU1452Z	ADI	获取价格	SigmaDSP Digital Audio Processor
EVAL-ADAU1701EB	ADI	获取价格	SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
EVAL-ADAU1702EB	ADI	获取价格	SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs
EVAL-ADAU1761Z	ADI	获取价格	SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
EVAL-ADAU1781Z	ADI	获取价格	Low Noise Stereo Codec with SigmaDSP Processing Core
EVAL-ADAU1966Z	ADI	获取价格	16-Channel High Performance
EVAL-ADAU1977Z	ADI	获取价格	Quad ADC with Diagnostics
EVAL-ADAU1978Z	ADI	获取价格	Quad Analog-to-Digital Converter (ADC)
EVAL-ADAU1979Z	ADI	获取价格	Quad Analog-to-Digital Converter (ADC)

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