Differential Input, Dual 1 MSPS,
12-Bit, 3-Channel SAR ADC
Preliminary Technical Data
AD7265
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Dual 12-bit, 3-channel ADC
AVdd DVdd
D
A
REF SELECT
cap
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power: 7 mW max at 1 MSPS with 3 V supplies
16.5 mW max at 1 MSPS with 5 V supplies
Wide input bandwidth
BUF
REF
AD7265
V
V
A1
12-BIT
OUTPUT
DRIVERS
SUCCESSIVE
APPROXIMATION
ADC
D
A
T/H
A2
OUT
MUX
V
A3
70 dB SNR at 100 kHz input frequency
On-chip reference: 2.5 V
SCLK
V
A4
CS
–40°C to +125°C operation
V
RANGE
A5
CONTROL
LOGIC
DIFF/SE
A0
A1
Flexible power/throughput rate management
Simultaneous conversion/read
No pipeline delays
V
A6
A2
V
B1
V
V
V
High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP
compatible
Shutdown mode: 1 µA max
DRIVE
B2
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
B3
B4
T/H
D
B
OUT
V
MUX
32-lead LFCSP and TQFP packages
V
V
B5
B6
BUF
GENERAL DESCRIPTION
The AD7265 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features throughput rates up to 1 MSPS. The
device contains two ADCs, each preceded by a 3-channel multi-
plexer, and a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 10 MHz.
D
B
AGND AGND AGND
DGND
DGND
cap
Figure 1
PRODUCT HIGHLIGHTS
1. The AD7265 features two complete ADC functions that allow
simultaneous sampling and conversion of two channels. Each
ADC has 2 analog inputs, 3 fully differential pairs, or 6 single-
ended channels as programmed. The conversion result of both
channels is available simultaneously on separate data lines, or
in succession on one data line if only one serial port is
available.
The conversion process and data acquisition are controlled using
standard control inputs, allowing easy interfacing to microproces-
CS
sors or DSPs. The input signal is sampled on the falling edge of
conversion is also initiated at this point. The conversion time is
;
determined by the SCLK frequency. There are no pipelined delays
associated with the part.
2. High Throughput with Low Power Consumption
The AD7265 offers a 1 MSPS throughput rate with ? mW
maximum power consumption when operating at 3 V.
The AD7265 uses advanced design techniques to achieve very low
power dissipation at high throughput rates. With 5 V supplies and a
1 MSPS throughput rate, the part consumes ? mA maximum. The
part also offers flexible power/throughput rate management when
operating in sleep mode.
3. Flexible Power/Throughput Rate Management
The conversion rate is determined by the serial clock, allowing
power consumption to be reduced as conversion time is re-
duced through an SCLK frequency increase. Power efficiency
can be maximized at lower throughput rates if the part enters
sleep between conversions.
The analog input range for the part can be selected to be a 0 V to
VREF range or a 2VREF range with either straight binary or twos
complement output coding. The AD7265 has an on-chip 2.5 V
reference that can be overdriven if an external reference is pre-
ferred. This external reference range is 100 mV to 2.5 V. The
AD7265 is available in 32-lead lead frame chip scale (LFCSP) and
thin flat quad (TQFP) lead package.
4. No Pipeline Delay
The part features two standard successive approximation
ADCs with accurate control of the sampling instant via a
input and once off conversion control.
CS
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
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