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EVAL-AD73360EZ PDF预览

EVAL-AD73360EZ

更新时间: 2024-11-30 22:49:07
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
35页 280K
描述
Six-Input Channel Analog Front End

EVAL-AD73360EZ 数据手册

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Six-Input Channel  
Analog Front End  
a
AD73360  
FEATURES  
Six 16-Bit A/D Converters  
Programmable Input Sample Rate  
Simultaneous Sampling  
77 dB SNR  
64 kS/s Maximum Sample Rate  
–83 dB Crosstalk  
Low Group Delay (25 s Typ per ADC Channel)  
Programmable Input Gain  
Flexible Serial Port which Allows Multiple Devices to  
Be Connected in Cascade  
Single (+2.7 V to +5.5 V) Supply Operation  
80 mW Max Power Consumption at +2.7 V  
On-Chip Reference  
metering or multichannel analog inputs. It features six 16-bit  
A/D conversion channels each of which provide 77 dB signal-to-  
noise ratio over a dc to 4 kHz signal bandwidth. Each channel  
also features a programmable input gain amplifier (PGA) with  
gain settings in eight stages from 0 dB to 38 dB.  
The AD73360 is particularly suitable for industrial power me-  
tering as each channel samples synchronously, ensuring that there  
is no (phase) delay between the conversions. The AD73360 also  
features low group delay conversions on all channels.  
An on-chip reference voltage is included and is programmable  
to accommodate either 3 V or 5 V operation.  
The sampling rate of the device is programmable with four  
separate settings offering 64 kHz, 32 kHz, 16 kHz and 8 kHz  
sampling rates (from a master clock of 16.384 MHz).  
28-Lead SOIC and 44-Lead TQFP Packages  
APPLICATIONS  
A serial port (SPORT) allows easy interfacing of single or cas-  
caded devices to industry standard DSP engines. The SPORT  
transfer rate is programmable to allow interfacing to both fast  
and slow DSP engines.  
General Purpose Analog Input  
Industrial Power Metering  
Motor Control  
Simultaneous Sampling Applications  
The AD73360 is available in 28-lead SOIC and 44-lead TQFP  
packages.  
GENERAL DESCRIPTION  
The AD73360 is a six-input channel analog front-end processor  
for general purpose applications including industrial power  
FUNCTIONAL BLOCK DIAGRAM  
VINP1  
VINN1  
ANALOG  
SIGNAL  
0/38dB  
PGA  
DECIMATOR  
SDI  
-⌬  
CONDITIONING  
MODULATOR  
SDIFS  
SCLK  
VINP2  
VINN2  
ANALOG  
-⌬  
MODULATOR  
SIGNAL  
CONDITIONING  
0/38dB  
PGA  
DECIMATOR  
DECIMATOR  
VINP3  
VINN3  
ANALOG  
-⌬  
MODULATOR  
SIGNAL  
CONDITIONING  
0/38dB  
PGA  
RESET  
MCLK  
SE  
REFERENCE  
REFCAP  
REFOUT  
SERIAL  
I/O  
PORT  
AD73360  
VINP4  
VINN4  
ANALOG  
-⌬  
SIGNAL  
0/38dB  
PGA  
DECIMATOR  
DECIMATOR  
DECIMATOR  
CONDITIONING  
MODULATOR  
VINP5  
VINN5  
ANALOG  
-⌬  
MODULATOR  
SIGNAL  
CONDITIONING  
0/38dB  
PGA  
SDO  
SDOFS  
VINP6  
VINN6  
ANALOG  
-⌬  
MODULATOR  
SIGNAL  
CONDITIONING  
0/38dB  
PGA  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2000  

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