Dual Low Power CMOS
Analog Front End with DSP Microcomputer
a
AD73422
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
FEATURES
AFE PERFORMANCE
Two 16-Bit A/D Converters
Two 16-Bit D/A Converters
Programmable Input/Output Sample Rates
78 dB ADC SNR
FULL MEMORY
MODE
CONTROL
DATA
MEMORY
PROGRAMMABLE
ADDRESS
EXTERNAL
ADDRESS
BUS
16K PM
(OPTIONAL (OPTIONAL
8K) 8K)
16K DM
PROGRAM
SEQUENCER
I/O
GENERATORS
AND
FLAGS
DAG 1 DAG 2
EXTERNAL
DATA
77 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BUS
BYTE DMA
CONTROLLER
Low Group Delay (25 s Typ per ADC Channel,
50 s Typ per DAC Channel)
Programmable Input/Output Gain
On-Chip Reference
PROGRAM MEMORY DATA
DATA MEMORY DATA
OR
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
TIMER
INTERNAL
DMA
PORT
SPORT 0 SPORT 1
DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
ADSP-2100 BASE
ARCHITECTURE
HOST MODE
SERIAL PORT
SPORT 2
REF
ADC1
DAC1
ADC2
DAC2
ANALOG FRONT END
SECTION
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
applications. The A/D and D/A conversion channels feature
programmable input/output gains with ranges 38 dB and 21 dB
respectively. An on-chip reference voltage is included to allow
single supply operation.
Low Power Dissipation in Idle Mode
GENERAL DESCRIPTION
The AD73422 is a single device incorporating a dual analog
front end and a microcomputer optimized for digital signal
processing (DSP) and other high speed numeric processing
applications.
The sampling rate of the AFE is programmable with four sepa-
rate settings offering 64, 32, 16 and 8 kHz sampling rates (from
a master clock of 16.384 MHz), while the serial port (SPORT2)
allows easy expansion of the number of I/O channels by cascad-
ing extra AFEs external to the AD73422.
The AD73422’s analog front end (AFE) section features a dual
front-end converter for general purpose applications including
speech and telephony. The AFE section features two 16-bit A/D
conversion channels and two 16-bit D/A conversion channels.
Each channel provides 77 dB signal-to-noise ratio over a
voiceband signal bandwidth. It also features an input-to-output
gain network in both the analog and digital domains. This is
featured on both codecs and can be used for impedance match-
ing or scaling when interfacing to Subscriber Line Interface
Circuits (SLICs).
The AD73422’s DSP engine combines the ADSP-2100 family
base architecture (three computational units, data address gen-
erators and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities and on-chip program
and data memory.
The AD73422-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. The AD73422-40 integrates 40K
bytes of on-chip memory configured as 8K words (24-bit) of
program RAM, and 8K words (16-bit) of data RAM. Power-
down circuitry is also provided to meet the low power needs of
battery operated portable equipment. The AD73422 is available
in a 119-ball PBGA package.
The AD73422 is particularly suitable for a variety of applica-
tions in the speech and telephony area including low bit rate,
high quality compression, speech enhancement, recognition
and synthesis. The low group delay characteristic of the AFE
makes it suitable for single or multichannel active control
REV. 0
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which may result from its use. No license is granted by implication or
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© Analog Devices, Inc., 1999