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EVAL-AD7440CB3 PDF预览

EVAL-AD7440CB3

更新时间: 2024-12-01 12:53:55
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亚德诺 - ADI /
页数 文件大小 规格书
28页 784K
描述
Differential Input, 1 MSPS ADCs in an 8-Lead SOT-23

EVAL-AD7440CB3 数据手册

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Differential Input, 1 MSPS  
10-Bit and 12-Bit ADCs in an 8-Lead SOT-23  
AD7440/AD7450A  
FUNCTIONAL BLOCK DIAGRAM  
DD  
FEATURES  
V
Fast throughput rate: 1 MSPS  
Specified for VDD of 3 V and 5 V  
Low power at max throughput rate  
4 mW max at 1 MSPS with 3 V supplies  
9.25 mW max at 1 MSPS with 5 V supplies  
Fully differential analog input  
Wide input bandwidth  
V
V
IN+  
12-BIT  
SUCCESSIVE  
APPROXIMATION  
ADC  
T/H  
IN–  
V
REF  
70 dB SINAD at 100 kHz input frequency  
Flexible power/serial clock speed management  
No pipeline delays  
SCLK  
SDATA  
High speed serial interface  
AD7440/AD7450A  
CONTROL LOGIC  
CS  
SPI®/QSPI™/MICROWIRE™/DSP compatible  
Power-down mode: 1 μA max  
8-lead SOT-23 and MSOP packages  
GND  
APPLICATIONS  
Figure 1.  
Transducer interface  
Battery-powered systems  
Data acquisition systems  
Portable instrumentation  
Motor control  
CS  
on the falling edge of ; the conversion is also initiated at this  
point. The SAR architecture of these parts ensures that there are  
no pipeline delays. The AD7440 and the AD7450A use ad-  
vanced design techniques to achieve very low power dissipation  
at high throughput rates.  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The AD7440/AD7450A1 are 10-bit and 12-bit high speed, low  
power, successive approximation (SAR) analog-to-digital  
converters with a fully differential analog input. These parts  
operate from a single 3 V or 5 V power supply and use  
advanced design techniques to achieve very low power  
dissipation at throughput rates up to 1 MSPS. The SAR  
architecture of these parts ensures that there are no pipeline  
delays.  
1. Operation with either 3 V or 5 V power supplies.  
2. High throughput with low power consumption.  
With a 3 V supply, the AD7440/AD7450A offer 4 mW  
max power consumption for 1 MSPS throughput.  
3. Fully differential analog input.  
4. Flexible power/serial clock speed management.  
The conversion rate is determined by the serial clock,  
allowing the power to be reduced as the conversion time  
is reduced through the serial clock speed increase. These  
parts also feature a shutdown mode to maximize power  
efficiency at lower throughput rates.  
The parts contain a low noise, wide bandwidth, differential  
track-and-hold amplifier (T/H) that can handle input  
frequencies up to 3.5 MHz. The reference voltage is applied  
externally to the VREF pin and can be varied from 100 mV to  
3.5 V depending on the power supply and what suits the  
application. The value of the reference voltage determines the  
common-mode voltage range of the part. With this truly  
differential input structure and variable reference input, the  
user can select a variety of input ranges and bias points.  
5. Variable voltage reference input.  
6. No pipeline delay.  
CS  
7. Accurate control of the sampling instant via a  
once-off conversion control.  
input and  
8. ENOB > eight bits typically with 100 mV reference.  
1 Protected by U.S. Patent Number 6,681,332.  
The conversion process and data acquisition are controlled  
CS  
using  
and the serial clock, allowing the device to interface  
with microprocessors or DSPs. The input signals are sampled  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  

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