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ESD7102 PDF预览

ESD7102

更新时间: 2022-02-26 14:02:35
品牌 Logo 应用领域
安森美 - ONSEMI 微控制器
页数 文件大小 规格书
6页 437K
描述
null8-bit Withstand Voltage Microcontroller

ESD7102 数据手册

 浏览型号ESD7102的Datasheet PDF文件第1页浏览型号ESD7102的Datasheet PDF文件第2页浏览型号ESD7102的Datasheet PDF文件第4页浏览型号ESD7102的Datasheet PDF文件第5页浏览型号ESD7102的Datasheet PDF文件第6页 
ESD7102, SZESD7102  
IEC61000−4−2 Waveform  
IEC 61000−4−2 Spec.  
I
peak  
First Peak  
Current  
(A)  
100%  
90%  
Test Volt-  
age (kV)  
Current at  
30 ns (A)  
Current at  
60 ns (A)  
Level  
1
2
3
4
2
4
6
8
7.5  
15  
4
8
2
4
6
8
I @ 30 ns  
22.5  
30  
12  
16  
I @ 60 ns  
10%  
t
P
= 0.7 ns to 1 ns  
Figure 5. IEC61000−4−2 Spec  
Oscilloscope  
ESD Gun  
TVS  
50 W  
Cable  
50 W  
Figure 6. Diagram of ESD Clamping Voltage Test Setup  
The following is taken from Application Note  
AND8308/D − Interpretation of Datasheet Parameters  
for ESD Devices.  
systems such as cell phones or laptop computers it is not  
clearly defined in the spec how to specify a clamping voltage  
at the device level. ON Semiconductor has developed a way  
to examine the entire voltage waveform across the ESD  
protection diode over the time domain of an ESD pulse in the  
form of an oscilloscope screenshot, which can be found on  
the datasheets for all ESD protection diodes. For more  
information on how ON Semiconductor creates these  
screenshots and how to interpret them please refer to  
AND8307/D.  
ESD Voltage Clamping  
For sensitive circuit elements it is important to limit the  
voltage that an IC will be exposed to during an ESD event  
to as low a voltage as possible. The ESD clamping voltage  
is the voltage drop across the ESD protection diode during  
an ESD event per the IEC61000−4−2 waveform. Since the  
IEC61000−4−2 was written as a pass/fail spec for larger  
www.onsemi.com  
3

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