Datasheet > EPM2210

EPM2210

更新时间： 2024-09-08 21:54:23

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
10页	104K
描述
JTAG & In-System Programmability

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EPM2210 数据手册

Chapter 3. JTAG & In-System

Programmability

MII51003-1.1

All MAX^®II devices provide Joint Test Action Group (JTAG) boundary-

scan test (BST) circuitry that complies with the IEEE Std. 1149.1-2001

specification. JTAG boundary-scan testing can only be performed at any

time after V_CCINTand all V_CCIObanks have been fully powered and a

t_CONFIGamount of time has passed. MAX II devices can also use the JTAG

IEEE Std. 1149.1

(JTAG)Boundary

Scan Support

port for in-system programming together with either the Quartus II

software or hardware using Programming Object Files (.pof), Jam

Standard Test and Programming Language (STAPL) Files (.jam) or Jam

Byte-Code Files (.jbc).

The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The

supported voltage level and standard is determined by the V_CCIOof the

bank where it resides. The dedicated JTAG pins reside in Bank 1 of all

MAX II devices.

MAX II devices support the JTAG instructions shown in Table 3–1.

Table 3–1. MAX II JTAG Instructions (Part 1 of 2)

JTAG Instruction

Instruction Code

Description

SAMPLE/PRELOAD

00 0000 0101

Allows a snapshot of signals at the device pins to be captured

and examined during normal device operation, and permits an

initial data pattern to be output at the device pins.

EXTEST(1)

00 0000 1111

11 1111 1111

Allows the external circuitry and board-level interconnects to

be tested by forcing a test pattern at the output pins and

capturing test results at the input pins.

BYPASS

Places the 1-bit bypass register between the TDIand TDO

pins, which allows the boundary scan test data to pass

synchronously through selected devices to adjacent devices

during normal device operation.

USERCODE

IDCODE

00 0000 0111

00 0000 0110

Selects the 32-bit USERCODEregister and places it between

the TDIand TDOpins, allowing the USERCODEto be serially

shifted out of TDO. This register defaults to all 1’s if not

specified in the Quartus II software.

Selects the IDCODEregister and places it between TDIand

TDO, allowing the IDCODE to be serially shifted out of TDO.

Altera Corporation

June 2004

Core Version a.b.c variable

3–1

Preliminary

12 3 4 5 6 7...10

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与EPM2210相关器件

型号	品牌	获取价格	描述	数据表
EPM2210100C5N	ALTERA	获取价格	The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m,
EPM2210F100A	ALTERA	获取价格	MAX II Device Family
EPM2210F100C	ALTERA	获取价格	MAX II Device Family
EPM2210F100C3ES	INTEL	获取价格	Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, FBGA-100
EPM2210F100C4N	INTEL	获取价格	Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100
EPM2210F100I	ALTERA	获取价格	MAX II Device Family
EPM2210F100I3ES	INTEL	获取价格	Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, FBGA-100
EPM2210F100I4N	INTEL	获取价格	Flash PLD, PBGA100, 11 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-100
EPM2210F256A3	INTEL	获取价格	Flash PLD, 7ns, 1700-Cell, CMOS, PBGA256
EPM2210F256A3N	ALTERA	获取价格	Flash PLD, 7ns, 1700-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, FBGA-256