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EPF6016ATI100-3 PDF预览

EPF6016ATI100-3

更新时间: 2024-01-21 16:04:28
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟输入元件可编程逻辑
页数 文件大小 规格书
52页 393K
描述
Loadable PLD, CMOS, PQFP100, TQFP-100

EPF6016ATI100-3 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:QFP包装说明:LFQFP, QFP100,.63SQ,20
针数:100Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.68其他特性:ALSO CONFIGURABLE WITH 5V VCC
最大时钟频率:133 MHzJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
湿度敏感等级:3专用输入次数:4
I/O 线路数量:81输入次数:81
逻辑单元数量:1320输出次数:81
端子数量:100组织:4 DEDICATED INPUTS, 81 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):220电源:2.5/3.3,3.3 V
可编程逻辑类型:LOADABLE PLD认证状态:Not Qualified
座面最大高度:1.27 mm子类别:Field Programmable Gate Arrays
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

EPF6016ATI100-3 数据手册

 浏览型号EPF6016ATI100-3的Datasheet PDF文件第3页浏览型号EPF6016ATI100-3的Datasheet PDF文件第4页浏览型号EPF6016ATI100-3的Datasheet PDF文件第5页浏览型号EPF6016ATI100-3的Datasheet PDF文件第7页浏览型号EPF6016ATI100-3的Datasheet PDF文件第8页浏览型号EPF6016ATI100-3的Datasheet PDF文件第9页 
FLEX 6000 Programmable Logic Device Family Data Sheet  
Figure 1. OptiFLEX Architecture Block Diagram  
IOEs  
Row FastTrack  
Interconnect  
Row FastTrack  
Interconnect  
Column FastTrack  
Interconnect  
IOEs  
Column FastTrack  
Interconnect  
Local Interconnect  
(Each LAB accesses  
two local interconnect  
areas.)  
Logic Elements  
FLEX 6000 devices provide four dedicated, global inputs that drive the  
control inputs of the flipflops to ensure efficient distribution of high-  
speed, low-skew control signals. These inputs use dedicated routing  
channels that provide shorter delays and lower skews than the FastTrack  
Interconnect. These inputs can also be driven by internal logic, providing  
an ideal solution for a clock divider or an internally generated  
asynchronous clear signal that clears many registers in the device. The  
dedicated global routing structure is built into the device, eliminating the  
need to create a clock tree.  
Logic Array Block  
An LAB consists of ten LEs, their associated carry and cascade chains, the  
LAB control signals, and the LAB local interconnect. The LAB provides  
the coarse-grained structure of the FLEX 6000 architecture, and facilitates  
efficient routing with optimum device utilization and high performance.  
6
Altera Corporation  

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