Datasheet > EPF6016AFC256-3

EPF6016AFC256-3

更新时间： 2024-02-04 22:20:50

品牌	Logo	应用领域
阿尔特拉 - ALTERA		时钟 LTE 栅输入元件可编程逻辑
页数	文件大小	规格书
52页	375K
描述
Loadable PLD, CMOS, PBGA256, FINE LINE, BGA-256

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EPF6016AFC256-3 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	BGA
包装说明：	BGA,	针数：	256
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.14	最大时钟频率：	133 MHz
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e1
长度：	17 mm	专用输入次数：	4
I/O 线路数量：	171	端子数量：	256
最高工作温度：	85 °C	最低工作温度：
组织：	4 DEDICATED INPUTS, 171 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	260	可编程逻辑类型：	LOADABLE PLD
认证状态：	Not Qualified	座面最大高度：	2.1 mm
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
温度等级：	OTHER	端子面层：	TIN SILVER COPPER
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	17 mm	Base Number Matches：	1

EPF6016AFC256-3 数据手册

FLEX 6000 Programmable Logic Device Family Data Sheet

The FLEX 6000 OptiFLEX architecture consists of logic elements (LEs).

Each LE includes a 4-input look-up table (LUT), which can implement any

4-input function, a register, and dedicated paths for carry and cascade

chain functions. Because each LE contains a register, a design can be easily

pipelined without consuming more LEs. The specified gate count for

FLEX 6000 devices includes all LUTs and registers.

Functional

Description

LEs are combined into groups called logic array blocks (LABs); each LAB

contains 10 LEs. The Altera software automatically places related LEs into

the same LAB, minimizing the number of required interconnects. Each

LAB can implement a medium-sized block of logic, such as a counter or

multiplexer.

Signal interconnections within FLEX 6000 devices—and to and from

device pins—are provided via the routing structure of the FastTrack

Interconnect. The routing structure is a series of fast, continuous row and

column channels that run the entire length and width of the device. Any

LE or pin can feed or be fed by any other LE or pin via the FastTrack

Interconnect. See “FastTrack Interconnect” on page 17 of this data sheet

for more information.

Each I/O pin is fed by an I/O element (IOE) located at the end of each row

and column of the FastTrack Interconnect. Each IOE contains a

bidirectional I/O buffer. Each IOE is placed next to an LAB, where it can

be driven by the local interconnect of that LAB. This feature allows fast

clock-to-output times of less than 8 ns when a pin is driven by any of the

10 LEs in the adjacent LAB. Also, any LE can drive any pin via the row and

column interconnect. I/O pins can drive the LE registers via the row and

column interconnect, providing setup times as low as 2 ns and hold times

of 0 ns. IOEs provide a variety of features, such as JTAG BST support,

slew-rate control, and tri-state buffers.

Figure 1 shows a block diagram of the FLEX 6000 OptiFLEX architecture.

Each group of ten LEs is combined into an LAB, and the LABs are

arranged into rows and columns. The LABs are interconnected by the

FastTrack Interconnect. IOEs are located at the end of each FastTrack

Interconnect row and column.

Altera Corporation

1 2 3 456 7 8...52

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与EPF6016AFC256-3相关器件

型号	品牌	描述	获取价格	数据表
EPF6016AFI100-3	INTEL	Loadable PLD, CMOS, PBGA100, FINE LINE, BGA-100	获取价格
EPF6016AFI256-1	ALTERA	Loadable PLD, CMOS, PBGA256, FINE LINE, BGA-256	获取价格
EPF6016AFI256-2	INTEL	Loadable PLD, CMOS, PBGA256, FINE LINE, BGA-256	获取价格
EPF6016AQC208-2	ALTERA	Programmable Logic Device Family	获取价格
EPF6016AQC208-3	ALTERA	Loadable PLD, CMOS, PQFP208, PLASTIC, QFP-208	获取价格
EPF6016AQC208-3N	ALTERA	Loadable PLD, CMOS, PQFP208, PLASTIC, QFP-208	获取价格

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