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EPF6016AFC256-3 PDF预览

EPF6016AFC256-3

更新时间: 2024-01-12 07:08:04
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟LTE输入元件可编程逻辑
页数 文件大小 规格书
52页 375K
描述
Loadable PLD, CMOS, PBGA256, FINE LINE, BGA-256

EPF6016AFC256-3 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:256
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.14最大时钟频率:133 MHz
JESD-30 代码:S-PBGA-B256JESD-609代码:e1
长度:17 mm专用输入次数:4
I/O 线路数量:171端子数量:256
最高工作温度:85 °C最低工作温度:
组织:4 DEDICATED INPUTS, 171 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):260可编程逻辑类型:LOADABLE PLD
认证状态:Not Qualified座面最大高度:2.1 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:OTHER端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:17 mmBase Number Matches:1

EPF6016AFC256-3 数据手册

 浏览型号EPF6016AFC256-3的Datasheet PDF文件第3页浏览型号EPF6016AFC256-3的Datasheet PDF文件第4页浏览型号EPF6016AFC256-3的Datasheet PDF文件第5页浏览型号EPF6016AFC256-3的Datasheet PDF文件第7页浏览型号EPF6016AFC256-3的Datasheet PDF文件第8页浏览型号EPF6016AFC256-3的Datasheet PDF文件第9页 
FLEX 6000 Programmable Logic Device Family Data Sheet  
Figure 1. OptiFLEX Architecture Block Diagram  
IOEs  
Row FastTrack  
Interconnect  
Row FastTrack  
Interconnect  
Column FastTrack  
Interconnect  
IOEs  
Column FastTrack  
Interconnect  
Local Interconnect  
(Each LAB accesses  
two local interconnect  
areas.)  
Logic Elements  
FLEX 6000 devices provide four dedicated, global inputs that drive the  
control inputs of the flipflops to ensure efficient distribution of high-  
speed, low-skew control signals. These inputs use dedicated routing  
channels that provide shorter delays and lower skews than the FastTrack  
Interconnect. These inputs can also be driven by internal logic, providing  
an ideal solution for a clock divider or an internally generated  
asynchronous clear signal that clears many registers in the device. The  
dedicated global routing structure is built into the device, eliminating the  
need to create a clock tree.  
Logic Array Block  
An LAB consists of ten LEs, their associated carry and cascade chains, the  
LAB control signals, and the LAB local interconnect. The LAB provides  
the coarse-grained structure of the FLEX 6000 architecture, and facilitates  
efficient routing with optimum device utilization and high performance.  
6
Altera Corporation  

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