EL4585

更新时间： 2024-09-17 22:49:11

品牌	Logo	应用领域
ELANTEC		/
页数	文件大小	规格书
16页	264K
描述
Horizontal Genlock, 8 FSC

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EL4585 数据手册

EL4585C

Horizontal Genlock, 8 F

Features

# 36 MHz, general purpose PLL

General Description

The EL4585C is a PLL (Phase Lock Loop) sub system, designed

for video applications, but also suitable for general purpose use

up to 36 MHz. In a video application this device generates a

TTL/CMOS compatible Pixel Clock (Clk Out) which is a multi-

ple of the TV Horizontal scan rate, and phase locked to it.

# 8 F timing. (Use the EL4584

for 4 F

)

# Compatible with EL4583C Sync

Separator

The reference signal is a horizontal sync signal, TTL/CMOS

format, which can be easily derived from an analog composite

video signal with the EL4583 Sync Separator. An input signal

to ‘‘coast’’ is provided for applications where periodic distur-

bances are present in the reference video timing such as VTR

head switching. The Lock detector output indicates correct lock.

# VCXO, Xtal, or LC tank

oscillator

2nS jitter (VCXO)

# User-controlled PLL capture and

lock

# Compatible with NTSC and PAL

TV formats

The divider ratio is four ratios for NTSC and four similar ratios

for the PAL video timing standards, by external selection of

three control pins. These four ratios have been selected for com-

# 8 pre-programmed popular TV

scan rate clock divisors

mon video applications including 8 F , 6 F , 27 MHz (CCIR

601 format) and square picture elements used in some worksta-

tion graphics. To generate 4 F , 3 F , 13.5 MHz (CCIR 601

# Single 5V, low current operation

Applications

# Pixel Clock regeneration

format) etc., use the EL4584, which does not have the addition-

al divide by 2 stage of the EL4585.

# Video compression engine

(MPEG) clock generator

For applications where these frequencies are inappropriate or

for general purpose PLL applications the internal divider can be

by passed and an external divider chain used.

# Video Capture or digitization

# PIP (Picture In Picture) timing

generator

FREQUENCIES and DIVISORS

Function

Divisor*

PAL Fosc (MHz)

6Fsc

CCIR 601

Square

8Fsc

# Text or Graphics overlay timing

1702

1728

27.0

1888

29.5

2270

Ordering Information

Package Outline

26.602

35.468

Part No.

Temp. Range

Divisor*

NTSC Fosc (MHz)

1364

1716

27.0

1560

1820

EL4585CN

EL4585CS

40 C to 85 C 16-Pin DIP MDP0031

21.476

24.546

28.636

40 C to 85 C 16-Lead SO MDP0027

CCIR 601 divisors yield 1440 pixels in the active portion of each line for NTSC and PAL.

Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL.

6Fsc frequencies do not yield integer divisors.

For 3Fsc and 4Fsc clock frequency operation,

see EL4584 datasheet.

*Divisor does not include

2 block.

Demo Board

A demo PCB is available for this

product. Request ‘‘EL4584/5 Demo

Board’’.

Connection Diagram

EL4585 SO, P-DIP Packages

4585–17

Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these

specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.

4585C

1995 Elantec, Inc.

12 3 4 5 6 7...16

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与EL4585相关器件

型号	品牌	获取价格	描述	数据表
EL4585C	ELANTEC	获取价格	Horizontal Genlock, 8 FSC
EL4585CN	ELANTEC	获取价格	Horizontal Genlock, 8 FSC
EL4585CN	INTERSIL	获取价格	Horizontal Genlock, 8FSC
EL4585CS	ELANTEC	获取价格	Horizontal Genlock, 8 FSC
EL4585CS	INTERSIL	获取价格	Horizontal Genlock, 8FSC
EL4585CS-T13	INTERSIL	获取价格	Horizontal Genlock, 8FSC
EL4585CS-T13	ELANTEC	获取价格	Video Clock Generator, 36MHz, CMOS, PDSO16, SO-16
EL4585CS-T7	INTERSIL	获取价格	Horizontal Genlock, 8FSC
EL4585CS-T7	ELANTEC	获取价格	Video Clock Generator, 36MHz, CMOS, PDSO16, SO-16
EL4585CSZ	INTERSIL	获取价格	Horizontal Genlock, 8FSC

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