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EL4585CS PDF预览

EL4585CS

更新时间: 2024-09-17 22:49:11
品牌 Logo 应用领域
ELANTEC 晶体时钟发生器微控制器和处理器外围集成电路光电二极管局域网
页数 文件大小 规格书
16页 264K
描述
Horizontal Genlock, 8 FSC

EL4585CS 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SO-16Reach Compliance Code:unknown
风险等级:5.75Is Samacsys:N
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:36 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:5 V
主时钟/晶体标称频率:36 MHz认证状态:Not Qualified
子类别:Other Microprocessor ICs标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALuPs/uCs/外围集成电路类型:CLOCK GENERATOR, VIDEO
Base Number Matches:1

EL4585CS 数据手册

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EL4585C  
Horizontal Genlock, 8 F  
SC  
Features  
# 36 MHz, general purpose PLL  
General Description  
The EL4585C is a PLL (Phase Lock Loop) sub system, designed  
for video applications, but also suitable for general purpose use  
up to 36 MHz. In a video application this device generates a  
TTL/CMOS compatible Pixel Clock (Clk Out) which is a multi-  
ple of the TV Horizontal scan rate, and phase locked to it.  
# 8 F timing. (Use the EL4584  
SC  
for 4 F  
)
SC  
# Compatible with EL4583C Sync  
Separator  
The reference signal is a horizontal sync signal, TTL/CMOS  
format, which can be easily derived from an analog composite  
video signal with the EL4583 Sync Separator. An input signal  
to ‘‘coast’’ is provided for applications where periodic distur-  
bances are present in the reference video timing such as VTR  
head switching. The Lock detector output indicates correct lock.  
# VCXO, Xtal, or LC tank  
oscillator  
k
#
2nS jitter (VCXO)  
# User-controlled PLL capture and  
lock  
# Compatible with NTSC and PAL  
TV formats  
The divider ratio is four ratios for NTSC and four similar ratios  
for the PAL video timing standards, by external selection of  
three control pins. These four ratios have been selected for com-  
# 8 pre-programmed popular TV  
scan rate clock divisors  
mon video applications including 8 F , 6 F , 27 MHz (CCIR  
SC  
SC  
601 format) and square picture elements used in some worksta-  
tion graphics. To generate 4 F , 3 F , 13.5 MHz (CCIR 601  
# Single 5V, low current operation  
SC  
SC  
Applications  
# Pixel Clock regeneration  
format) etc., use the EL4584, which does not have the addition-  
al divide by 2 stage of the EL4585.  
# Video compression engine  
(MPEG) clock generator  
For applications where these frequencies are inappropriate or  
for general purpose PLL applications the internal divider can be  
by passed and an external divider chain used.  
# Video Capture or digitization  
# PIP (Picture In Picture) timing  
generator  
FREQUENCIES and DIVISORS  
Function  
Divisor*  
PAL Fosc (MHz)  
6Fsc  
CCIR 601  
Square  
8Fsc  
# Text or Graphics overlay timing  
1702  
1728  
27.0  
1888  
29.5  
2270  
Ordering Information  
Package Outline  
26.602  
35.468  
Ý
Part No.  
Temp. Range  
Divisor*  
NTSC Fosc (MHz)  
1364  
1716  
27.0  
1560  
1820  
b
b
a
EL4585CN  
EL4585CS  
40 C to 85 C 16-Pin DIP MDP0031  
§
§
§
21.476  
24.546  
28.636  
a
40 C to 85 C 16-Lead SO MDP0027  
§
CCIR 601 divisors yield 1440 pixels in the active portion of each line for NTSC and PAL.  
Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL.  
6Fsc frequencies do not yield integer divisors.  
For 3Fsc and 4Fsc clock frequency operation,  
see EL4584 datasheet.  
d
*Divisor does not include  
2 block.  
Demo Board  
A demo PCB is available for this  
product. Request ‘‘EL4584/5 Demo  
Board’’.  
Connection Diagram  
EL4585 SO, P-DIP Packages  
458517  
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these  
Ý
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.  
4585C  
©
1995 Elantec, Inc.  

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