Datasheet > EL4585CSZ

EL4585CSZ

更新时间： 2024-09-17 22:49:11

品牌	Logo	应用领域
英特矽尔 - INTERSIL		晶体外围集成电路光电二极管 PC 时钟
页数	文件大小	规格书
12页	264K
描述
Horizontal Genlock, 8FSC

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EL4585CSZ 数据手册

EL4585

Data Sheet

July 1, 2005

FN7175.3

Horizontal Genlock, 8F

Features

• 36MHz, general purpose PLL

The EL4585 is a PLL (Phase Lock Loop) sub-system,

designed for video applications and also suitable for general

purpose use up to 36MHz. In video applications, this device

generates a TTL/CMOS-compatible pixel clock (CLK OUT)

which is a multiple of the TV horizontal scan rate and phase

locked to it.

• 8F timing (use the EL4584 for 4F

)

• Compatible with EL4583 sync separator

• VCXO, Xtal, or LC tank oscillator

• < 2ns jitter (VCXO)

The reference signal is a horizontal sync signal, TTL/CMOS

format, which can be easily derived from an analog

composite video signal with the EL4583 sync separator. An

input signal to “coast” is provided for applications where

periodic disturbances are present in the reference video

timing such as VTR head switching. The lock detector output

indicates correct lock.

• User-controlled PLL capture and lock

• Compatible with NTSC and PAL TV formats

• 8 pre-programmed popular TV scan rate clock divisors

• Single 5V, low current operation

• Pb-Free Plus Anneal Available (RoHS Compliant)

The divider ratio is four ratios for NTSC and four similar

ratios for the PAL video timing standards by external

selection of three control pins. These four ratios have been

Applications

• Pixel clock regeneration

selected for common video applications including 8F

• Video compression engine (MPEG) clock generator

• Video capture or digitization

6F , 27MHz (CCIR 601 format) and square picture

elements used in some workstation graphics. To generate

4F , 3F , 13.5MHz (CCIR 601 format) etc., use the

• PIP (Picture in Picture) timing generator

• Text or graphics overlay timing

EL4584, which does not have the additional divide-by-two

stage of the EL4585.

For applications where these frequencies are inappropriate

or for general purpose PLL applications the internal divider

can be bypassed and an external divider chain used.

Ordering Information

PART

TAPE &

REEL

PKG. DWG.

NUMBER

PACKAGE

16-Pin PDIP

FREQUENCIES AND DIVISORS

EL4585CN

EL4585CS

MDP0031

MDP0027

CCIR601 SQUARE

(NOTE 1) (NOTE 2) (NOTE 3)

16-Pin SO (0.150”)

FUNCTION

EL4585CS-T7

7”

13”

Divisor (Note 4)

1702

26.602

1364

1728

27.0

1716

27.0

1888

29.5

2270

35.468

1820

EL4585CS-T13 16-Pin SO (0.150”)

PAL F

(MHz)

Divisor (Note 4)

OSC

EL4585CSZ

(See Note)

16-Pin SO (0.150”)

(Pb-free)

1560

NTSC F

NOTES:

(MHz)

21.476

24.546

28.636

OSC

EL4585CSZ-T7 16-Pin SO (0.150”)

(See Note) (Pb-free)

7”

MDP0027

1. 6F

frequencies do not yield integer divisors.

EL4585CSZ-T13 16-Pin SO (0.150”)

(See Note) (Pb-free)

13”

2. CCIR 601 divisors yield 1440 pixels in the active portion of each

line for NTSC and PAL.

3. Square pixels format gives 640 pixels for NTSC and 768 pixels

for PAL.

*For 3F

and 4F

clock frequency operation, see EL4584

datasheet.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

4. Divisor does not include ÷ 2 block.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

12 3 4 5 6 7...12

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EL4585CSZ 替代型号

型号	品牌	替代类型	描述	数据表
EL4585CS-T13	INTERSIL	完全替代	Horizontal Genlock, 8FSC
EL4585CS	INTERSIL	完全替代	Horizontal Genlock, 8FSC
EL4585CSZ-T13	INTERSIL	完全替代	Horizontal Genlock, 8FSC

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