EL4584
®
Data Sheet
July 25, 2005
FN7174.2
Horizontal Genlock, 4F
Features
• 36MHz, general purpose PLL
SC
The EL4584 is a PLL (Phase Lock Loop) sub system,
designed for video applications but also suitable for general
purpose use up to 36MHz. In video applications, this device
generates a TTL/CMOS compatible Pixel Clock (CLK OUT)
which is a multiple of the TV horizontal scan rate and phase
locked to it.
• 4F based timing (use the EL4585 for 8F
)
SC
SC
• Compatible with EL4583 sync separator
• VCXO, Xtal, or LC tank oscillator
• < 2ns jitter (VCXO)
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog
composite video signal with the EL4583 Sync Separator. An
input signal to “coast” is provided for applications were
periodic disturbances are present in the reference video
timing such as VTR head switching. The Lock detector
output indicates correct lock.
• User controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed TV scan rate clock divisors
• Selectable external divide for custom ratios
• Single 5V, low current operation
The divider ratio is four ratios for NTSC and four similar
ratios for the PAL video timing standards, by external
selection of three control pins. These four ratios have been
• Pb-Free plus anneal available (RoHS compliant)
Applications
• Pixel clock regeneration
selected for common video applications including 4F
,
SC
3F , 13.5MHz (CCIR 601 format) and square picture
SC
elements used in some workstation graphics. To generate
• Video compression engine (MPEG) clock generator
• Video capture or digitization
8F , 6F , 27MHz (CCIR 601 format) etc. use the
SC
SC
EL4585, which includes an additional divide-by-two stage.
• PIP (Picture in Picture) timing generator
• Text or graphics overlay timing
For applications where these frequencies are inappropriate
or for general purpose PLL applications the internal divider
can be bypassed and an external divider chain used.
Ordering Information
FREQUENCIES AND DIVISORS
TAPE &
REEL
PKG. DWG.
3F
CCIR 601 SQUARE
(NOTE 1) (NOTE 2) (NOTE 3)
SC
PART NUMBER
EL4584CN
PACKAGE
16-Pin PDIP
#
FUNCTION
Divisor
PAL F
4F
SC
-
-
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
851
13.301
682
864
13.5
858
944
14.75
780
1135
17.734
910
EL4584CS
16-Pin SO (0.150”)
16-Pin SO (0.150”)
(MHz)
OSC
EL4584CS-T7
7”
13”
-
Divisor
NTSC F
NOTES:
EL4584CS-T13 16-Pin SO (0.150”)
MHz) 10.738
13.5
12.273
14.318
OSC
EL4584CSZ
(See Note)
16-Pin SO (0.150”)
(Pb-free)
1. 3F
numbers do not yield integer divisors.
SC
EL4584CSZ-T7 16-Pin SO (0.150”)
(See Note) (Pb-free)
7”
MDP0027
MDP0027
2. CCIR 601 Divisors yield 720 pixels in the portion of each line for
NTSC and PAL.
3. Square pixels format gives 640 pixels for NTSC and 768 pixels
for PAL in the active portion.
EL4584CSZ-T13 16-Pin SO (0.150”)
(See Note) (Pb-free)
13”
*For 6F
SC
and 8F
clock frequencies, see EL4585 datasheet.
SC
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb
and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Demo Board
A demo PCB is available for this product.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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