PRELIMINARY DATA SHEET
128M bits Mobile RAM
EDL1216CFBJ (8M words × 16 bits)
Specifications
Pin Configurations
• Density: 128M bits
/xxx indicates active low signal.
• Organization: 2M words × 16 bits × 4 banks
60-ball FBGA
• Package: 60-ball FBGA
1
2
3
4
5
6
7
8
9
10
Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.7V to 1.95V
• Clock frequency: 133MHz (max.)
• 1KB page size
Row address: A0 to A11
Column address: A0 to A8
• Four internal banks for concurrent operation
• Interface: LVCMOS
• Burst lengths (BL): 1, 2, 4, 8, full page
• Burst type (BT):
A
B
C
D
E
F
VDDQ DQ0 VDD
DQ1 DQ2 VSSQ
DQ3 DQ4 VDDQ
DQ5 DQ6 VSSQ
DQ7
VSS DQ15 VSSQ
DQ13 DQ14
VDDQ
VSSQ DQ11
VDDQ DQ9
DQ12
DQ10
NC
NC
NC DQ8
NC
Sequential (1, 2, 4, 8, full page)
Interleave (1, 2, 4, 8)
• /CAS Latency (CL): 3
NC LDQM
VDD
/RAS
NC
UDQM
VSS
CKE
A9
G
H
J
/CAS
/WE
CLK NC
• Precharge: auto precharge option for each burst
/CS BA0
A11
A7
BA1
A1
NC
A8
A5
access
• Driver strength: normal/weak
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/64ms
Average refresh period: 15.6µs
• Operating ambient temperature range
TA = –25°C to +85°C
A10/AP A0
A6
K
A4
VSS
A3
A2
VDD
(Top view)
A0 to A11
BA0, BA1
Address inputs
Bank select
DQ0 to DQ15 Data inputs/ outputs
Features
CLK
Clock input
CKE
/CS
/RAS
/CAS
/WE
Clock enable
Chip select
Row address strobe
Column address strobe
Write enable
• Low power consumption
• Single pulsed /RAS
• Burst read/write operation capability
• Byte control by DQM
• Programmable Partial Array Self-Refresh
UDQM
LDQM
VDD
VSS
VDDQ
VSSQ
NC
Upper DQ mask enable
Lower DQ mask enable
Power supply
Ground
Power supply for DQ
Ground for DQ
• Auto Temperature Compensated Self-Refresh
(ATCSR) by built-in temperature sensor
• Burst termination by burst stop command and
Precharge command
No connection
Document No. E1137E51 (Ver. 5.1)
Date Published August 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007-2008