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EDL5132CBMA PDF预览

EDL5132CBMA

更新时间: 2024-11-04 22:28:23
品牌 Logo 应用领域
尔必达 - ELPIDA /
页数 文件大小 规格书
62页 559K
描述
512M bits Mobile RAM MCP 2 pcs of 256Mb components (16M words x 32 bits)

EDL5132CBMA 数据手册

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PRELIMINARY DATA SHEET  
512M bits Mobile RAM MCP  
2 pcs of 256Mb components  
EDL5132CBMA (16M words × 32 bits)  
Description  
Pin Configurations  
The EDL5132CBMA is a 512M bits Mobile RAM MCP  
(Multi Chip Package) organized as 4,194,304 words ×  
32 bits × 4 banks, 2 pieces of 256M bits Mobile RAM in  
one package. It is packaged in 90-ball FBGA.  
/xxx indicates active low signal.  
90-ball FBGA  
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DQ26 DQ24 VSS  
DQ28 VDDQ VSSQ  
VSSQ DQ27 DQ25  
VSSQ DQ29 DQ30  
VDDQ DQ31 NC  
VSS DQM3 A3  
VDD DQ23 DQ21  
VDDQ VSSQ DQ19  
DQ22 DQ20 VDDQ  
DQ17 DQ18 VDDQ  
NC DQ16 VSSQ  
A2 DQM2 VDD  
Features  
Low voltage power supply  
VDD:  
1.7V to 1.95V  
VDDQ: 1.7V to 1.95V  
Wide temperature range (25°C to 85°C)  
Programmable Partial Array Self Refresh  
Programmable Driver Strength  
Auto Temperature Compensated Self Refresh by  
built-in temperature sensor.  
G
H
J
A4  
A7  
A5  
A8  
A6  
A12  
A9  
A10  
NC  
A0  
A1  
Deep power down mode  
BA1 A11  
Fully Synchronous Dynamic RAM, with all signals  
referenced to a positive clock edge  
CLK CKE  
DQM1 NC  
BA0 /CS /RAS  
/CAS /WE DQM0  
VDD DQ7 VSSQ  
DQ6 DQ5 VDDQ  
DQ1 DQ3 VDDQ  
VDDQ VSSQ DQ4  
VDD DQ0 DQ2  
K
L
Pulsed interface  
NC  
Possible to assert random column address in every  
cycle  
VDDQ DQ8 VSS  
VSSQ DQ10 DQ9  
VSSQ DQ12 DQ14  
DQ11 VDDQ VSSQ  
DQ13 DQ15 VSS  
Quad internal banks controlled by BA0 and BA1  
Byte control by DQM  
M
N
P
R
Wrap sequence = Sequential/ Interleave  
/CAS latency (CL) = 2, 3  
Automatic precharge and controlled precharge  
Auto refresh and self refresh  
• ×32 organization  
(Top view)  
8,192 refresh cycles/64ms  
A0 to A12  
BA0, BA1  
DQ0 to DQ31  
/CS  
/RAS  
/CAS  
Address inputs  
Bank select address  
Data-input/output  
Chip select  
Row address strobe  
Column address strobe  
Write enable  
Burst termination by Burst stop command and  
Precharge command  
FBGA package with lead free solder (Sn-Ag-Cu)  
/WE  
DQM0 to DQM3  
CKE  
DQ mask enable  
Clock enable  
CLK  
Clock input  
VDD  
Power supply  
VSS  
Ground  
VDDQ  
VSSQ  
NC  
Power supply for DQ  
Ground for DQ  
No connection  
Document No. E0490E30 (Ver. 3.0)  
Date Published September 2004 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2004  

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