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EDL6416CABH-10-E PDF预览

EDL6416CABH-10-E

更新时间: 2024-11-04 21:04:11
品牌 Logo 应用领域
尔必达 - ELPIDA 时钟动态存储器内存集成电路
页数 文件大小 规格书
58页 688K
描述
Synchronous DRAM, 4MX16, 6ns, CMOS, PBGA54, LEAD FREE, FBGA-54

EDL6416CABH-10-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA54,9X9,32
针数:54Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.84访问模式:FOUR BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:S-PBGA-B54
JESD-609代码:e1长度:8 mm
内存密度:67108864 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:54
字数:4194304 words字数代码:4000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-25 °C组织:4MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA54,9X9,32
封装形状:SQUARE封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.8 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.05 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.00001 A
子类别:DRAMs最大压摆率:0.06 mA
最大供电电压 (Vsup):1.95 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
Base Number Matches:1

EDL6416CABH-10-E 数据手册

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PRELIMINARY DATA SHEET  
64M bits Mobile RAM  
EDL6416CABH (4M words × 16 bits)  
Description  
Pin Configurations  
The EDL6416CABH is a 64M bits Mobile RAM  
/xxx indicates active low signal.  
54-ball FBGA  
organized as 1,048,576 words × 16 bits × 4 banks.  
The Mobile RAM achieved low power consumption  
and high-speed data transfer using the pipeline  
architecture.  
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
All inputs and outputs are synchronized with the  
VSS DQ15 VSSQ  
DQ14 DQ13 VDDQ  
DQ12 DQ11 VSSQ  
DQ10 DQ9 VDDQ  
VDDQ DQ0  
VSSQ DQ2  
VDDQ DQ4  
VSSQ DQ6  
VDD  
DQ1  
DQ3  
DQ5  
positive edge of the clock.  
This product is packaged in 54-ball FBGA.  
Features  
Low voltage power supply  
VDD:  
1.8V ± 0.15V  
VDDQ: 1.8V ± 0.15V  
DQ8  
NC  
VSS  
CKE  
A9  
VDD LDQM DQ7  
/CAS /RAS /WE  
Wide temperature range (25°C to 85°C)  
Programmable Partial Self Refresh  
Programmable Driver Strength  
UDQM CLK  
G
H
J
Advanced (Auto) Temperature Compensated Self  
NC  
A8  
A11  
A7  
BA0  
A0  
BA1  
A1  
/CS  
A10  
VDD  
Refresh  
Deep power down mode  
Small package (54-ball FBGA)  
A6  
VSS  
A5  
A4  
A3  
A2  
Fully Synchronous Dynamic RAM, with all signals  
referenced to a positive clock edge  
(Top view)  
Pulsed interface  
A0 to A11  
BA0, BA1  
Address inputs  
Bank select  
Possible to assert random column address in every  
cycle  
DQ0 to DQ15  
CLK  
Data inputs/ outputs  
Clock input  
Quad internal banks controlled by BA0 and BA1  
Byte control by LDQM and UDQM  
Wrap sequence = Sequential/ Interleave  
/CAS latency (CL) = 2, 3  
Automatic precharge and controlled precharge  
Auto refresh and self refresh  
CKE  
Clock enable  
/CS  
Chip select  
/RAS  
/CAS  
/WE  
Row address strobe  
Column address strobe  
Write enable  
• ×16 organization  
4,096 refresh cycles/64ms  
UDQM  
LDQM  
VDD  
Upper DQ mask enable  
Lower DQ mask enable  
Power supply  
Burst termination by Burst stop command and  
Precharge command  
VSS  
Ground  
FBGA package with lead free solder (Sn-Ag-Cu)  
VDDQ  
VSSQ  
NC  
Power supply for DQ  
Ground for DQ  
No connection  
Document No. E0422E30 (Ver. 3.0)  
Date Published April 2004 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2003-2004  

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T(Max.)=3.50mm