EDJ2104BASE-DJ-F

更新时间： 2024-11-28 11:45:07

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
148页	1780K
描述
2G bits DDR3 SDRAM

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中文翻译

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数据手册

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EDJ2104BASE-DJ-F 数据手册

PRELIMINARY DATA SHEET

2G bits DDR3 SDRAM

EDJ2104BASE (512M words × 4 bits)

EDJ2108BASE (256M words × 8 bits)

Features

Specifications

• Density: 2G bits

• Organization

64M words × 4 bits × 8 banks (EDJ2104BASE)

32M words × 8 bits × 8 banks (EDJ2108BASE)

• Package

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

78-ball FBGA

Lead-free (RoHS compliant) and Halogen-free

• Power supply: VDD, VDDQ = 1.5V ± 0.075V

• Data rate

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

1600Mbps/1333Mbps/1066Mbps/800Mbps (max.)

• 1KB page size

transitions

• Commands entered on each positive CK edge; data

Row address: A0 to A14

and data mask referenced to both edges of DQS

Column address: A0 to A9, A11 (EDJ2104BASE)

• Data mask (DM) for write data

A0 to A9 (EDJ2108BASE)

• Posted /CAS by programmable additive latency for

• Eight internal banks for concurrent operation

• Interface: SSTL_15

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

• Burst type (BT):

Sequential (8, 4 with BC)

Interleave (8, 4 with BC)

• /CAS Latency (CL): 6, 7, 8, 9, 10, 11

• /CAS Write Latency (CWL): 5, 6, 7, 8

better command and data bus efficiency

• On-Die Termination (ODT) for better signal quality

Synchronous ODT

Dynamic ODT

Asynchronous ODT

• Multi Purpose Register (MPR) for temperature read

out

• ZQ calibration for DQ drive and ODT

• Programmable Partial Array Self-Refresh (PASR)

• Precharge: auto precharge option for each burst

access

• /RESET pin for Power-up sequence and reset

• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

• Refresh: auto-refresh, self-refresh

• Refresh cycles

function

• SRT range:

Normal/extended

• Programmable Output driver impedance control

Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Operating case temperature range

TC = 0°C to +95°C

Document No. E1505E20 (Ver. 2.0)

Date Published November 2009 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2009

12 3 4 5 6 7...148

中文翻译

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与EDJ2104BASE-DJ-F相关器件

型号	品牌	获取价格	描述	数据表
EDJ2104BASE-GN-F	ELPIDA	获取价格	2G bits DDR3 SDRAM
EDJ2104BCSE-8C-F	ELPIDA	获取价格	DDR DRAM, 512MX4, 20ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
EDJ2104BCSE-AE-F	ELPIDA	获取价格	DDR DRAM, 512MX4, 20ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
EDJ2104BDBG	ELPIDA	获取价格	Differential clock inputs
EDJ2104BDBG-8C-F	ELPIDA	获取价格	Differential clock inputs
EDJ2104BDBG-AE-F	ELPIDA	获取价格	Differential clock inputs
EDJ2104BDBG-DJ-F	ELPIDA	获取价格	Differential clock inputs
EDJ2104BDBG-GN-F	ELPIDA	获取价格	Differential clock inputs
EDJ2104BDBG-JS-F	ELPIDA	获取价格	Differential clock inputs
EDJ2104EDBG	ELPIDA	获取价格	ZQ calibration for DQ drive and ODT

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