5秒后页面跳转
捷配首页

Datasheet > EDI88512CA35N36C
EDI88512CA35N36C PDF预览

EDI88512CA35N36C

更新时间： 2024-11-01 20:34:43
品牌 Logo 应用领域
美高森美 - MICROSEMI 静态存储器
页数 文件大小 规格书
10页 1108K
描述
Standard SRAM, 512KX8, 35ns, CMOS, CDSO36, CERAMIC, SOJ-36

阅读下载

中文翻译

获取价格

EDI88512CA35N36C 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Transferred零件包装代码：SOJ
包装说明：CERAMIC, SOJ-36针数：36
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.02
Is Samacsys：N最长访问时间：35 ns
其他特性：TTL COMPATIBLE INPUTS/OUTPUTSJESD-30 代码：R-CDSO-J36
长度：23.622 mm内存密度：4194304 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
功能数量：1端子数量：36
字数：524288 words字数代码：512000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512KX8
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：SOJ
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：3.937 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：11.1506 mmBase Number Matches：1

EDI88512CA35N36C 数据手册

 浏览型号EDI88512CA35N36C的Datasheet PDF文件第2页浏览型号EDI88512CA35N36C的Datasheet PDF文件第3页浏览型号EDI88512CA35N36C的Datasheet PDF文件第4页浏览型号EDI88512CA35N36C的Datasheet PDF文件第5页浏览型号EDI88512CA35N36C的Datasheet PDF文件第6页浏览型号EDI88512CA35N36C的Datasheet PDF文件第7页 
EDI88512CA  
512Kx8 Monolithic SRAM, SMD 5962-95600  
FEATURES  
 Access Times of 15, 17, 20, 25, 35, 45, 55ns  
 Data Retention Function (LPA version)  
 TTL Compatible Inputs and Outputs  
 Fully Static, No Clocks  
The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM.  
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard  
for the four megabit device. All 32 pin packages are pin for pin  
upgrades for the single chip enable 128K x 8, the EDI88128CS.  
Pins 1 and 30 become the higher order addresses.  
 Organized as 512Kx8  
The 36 pin revolutionary pinout also adheres to the JEDEC  
standard for the four megabit device. The center pin power and  
ground pins help to reduce noise in high performance systems.  
The 36 pin pinout also allows the user an upgrade path to the  
future 2Mx8.  
 Commercial, Industrial and Military Temperature Ranges  
 32 lead JEDEC Approved Evolutionary Pinout  
• Ceramic Sidebrazed 600 mil DIP (Package 9)  
• Ceramic Sidebrazed 400 mil DIP (Package 326)  
• Ceramic 32 pin Flatpack (Package 344)  
• Ceramic Thin Flatpack (Package 321)  
• Ceramic SOJ (Package 140)  
A Low Power version with Data Retention (EDI88512LPA) is  
also available for battery backed applications. Military product is  
available compliant to Appendix A of MIL-PRF-38535.  
 36 lead JEDEC Approved Revolutionary Pinout  
• Ceramic Flatpack (Package 316)  
*This product is subject to change without notice.  
• Ceramic SOJ (Package 327)  
• Ceramic LCC (Package 502)  
 Single +5V (±10%) Supply Operation  
FIGURE 1 – PIN CONFIGURATION  
PIN DESCRIPTION  
Data Inputs/Outputs  
Address Inputs  
Write Enables  
Chip Selects  
I/O0-7  
A0-18  
WE#  
CS#  
OE#  
VCC  
VSS  
Output Enable  
Power (+5V ±10%)  
Ground  
36 PIN  
32 PIN  
TOP VIEW  
TOP VIEW  
NC  
Not Connected  
1
2
36 NC  
35 A18  
34 A17  
33 A16  
32 A15  
31 OE#  
30 I/O7  
29 I/O6  
32 Vcc  
31 A15  
30 A17  
29 WE#  
28 A13  
27 A8  
A0  
A1  
A18  
A16  
A14  
A12  
A7  
1
2
3
A2  
3
4
A3  
4
BLOCK DIAGRAM  
5
A4  
5
6
CS#  
I/O0  
I/O1  
Vcc  
Vss  
I/O2  
I/O3  
WE#  
A5  
A6  
6
26 A9  
7
A5  
7
32 pin  
Evolutionary  
25 A11  
24 OE#  
23 A10  
22 CS#  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
8
8
A4  
36 pin  
Revolutionary  
Memory Array  
9
Vss  
Vcc  
I/O5  
I/O4  
A14  
A13  
A12  
A11  
A10  
NC  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
9
A3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
10  
11  
12  
13  
14  
A2  
A1  
A0  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
0-18  
I/O0-7  
I/O0  
I/O1  
A6  
I/O2 15  
A7  
Vss  
16  
WE#  
CS#  
OE#  
A8  
A9  
Microsemi Corporation reserves the right to change products or specifications without notice.  
February 2012 © 2012 Microsemi Corporation. All rights reserved.  
Rev. 14  
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com  
1234567...10

中文翻译

下载PDF

与EDI88512CA35N36C相关器件

型号 品牌 获取价格 描述 数据表
EDI88512CA35N36I MERCURY

获取价格

 		Standard SRAM, 512KX8, 35ns, CMOS, CDSO36, CERAMIC, SOJ-36
EDI88512CA35N36I MICROSEMI

获取价格

 		Standard SRAM, 512KX8, 35ns, CMOS, CDSO36, CERAMIC, SOJ-36
EDI88512CA35N36M MICROSEMI

获取价格

 		Standard SRAM, 512KX8, 35ns, CMOS, CDSO36, CERAMIC, SOJ-36
EDI88512CA35NB MERCURY

获取价格

 		Standard SRAM, 512KX8, 35ns, CMOS, CDSO32, CERAMIC, SOJ-32
EDI88512CA35NC ETC

获取价格

 		x8 SRAM
EDI88512CA35NI ETC

获取价格

 		x8 SRAM
EDI88512CA35NM ETC

获取价格

 		x8 SRAM
EDI88512CA35TB MERCURY

获取价格

 		Standard SRAM, 512KX8, 35ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88512CA35TB MICROSEMI

获取价格

 		Standard SRAM, 512KX8, 35ns, CMOS, CDIP32, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-32
EDI88512CA35TC ETC

获取价格

 		x8 SRAM

与EDI88512CA35N36C相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证