EBJ41HF4B1QA

更新时间： 2024-11-21 12:20:55

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
21页	227K
描述
4GB VLP Registered DDR3 SDRAM DIMM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EBJ41HF4B1QA 数据手册

DATA SHEET

4GB VLP Registered DDR3 SDRAM DIMM

EBJ41HF4B1QA (512M words × 72 bits, 2 Ranks)

Specifications

Features

• Density: 4GB

• Double-data-rate architecture; two data transfers per

clock cycle

• Organization

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

512M words × 72 bits, 2 ranks

• Mounting 18 pieces of 2G bits DDR3 SDRAM with

DDP (FBGA)

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

DDP: 2 pieces of 1G bits chips sealed in one

package

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Package: 240-pin very low profile dual in line

memory module (VLP DIMM)

• Differential clock inputs (CK and /CK)

PCB height: 18.75mm

• DLL aligns DQ and DQS transitions with CK

transitions

Lead pitch: 1.0mm

Lead-free (RoHS compliant)

• Power supply: VDD = 1.5V ± 0.075V

• Data rate: 1333Mbps/1066Mbps (max.)

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• Eight internal banks for concurrent operation

(components)

• On-Die-Termination (ODT) for better signal quality

Synchronous ODT

• Interface: SSTL_15

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

• /CAS Latency (CL): 6, 7, 8, 9

Dynamic ODT

Asynchronous ODT

• /CAS write latency (CWL): 5, 6, 7

• Multi Purpose Register (MPR) for temperature read

out

• Precharge: auto precharge option for each burst

access

• ZQ calibration for DQ drive and ODT

• Refresh: auto-refresh, self-refresh

• Refresh cycles

• Programmable Partial Array Self-Refresh (PASR)

• /RESET pin for Power-up sequence and reset

function

Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• SRT range:

Normal/extended

• Operating case temperature range

TC = 0°C to +95°C

Auto/manual self-refresh

• Programmable Output driver impedance control

• 1 piece of registering clock driver and 1 piece of

serial EEPROM (256 bytes EEPROM) for Presence

Detect (PD)

• Class B temperature sensor functionality with

EEPROM

Note: Warranty void if removed DIMM heat

spreader.

Document No. E1265E40 (Ver.4.0)

Date Published December 2008 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2008

12 3 4 5 6 7...21

中文翻译

下载PDF

与EBJ41HF4B1QA相关器件

型号	品牌	获取价格	描述	数据表
EBJ41HF4B1QA-AE-E	ELPIDA	获取价格	4GB VLP Registered DDR3 SDRAM DIMM
EBJ41HF4B1QA-DJ-E	ELPIDA	获取价格	4GB VLP Registered DDR3 SDRAM DIMM
EBJ41RE4BAFA-8A-E	ELPIDA	获取价格	DDR DRAM Module, 512MX72, 0.4ns, CMOS, ROHS COMPLIANT, DIMM-240
EBJ41RE4BAFA-8C-E	ELPIDA	获取价格	DDR DRAM Module, 512MX72, 0.4ns, CMOS, ROHS COMPLIANT, DIMM-240
EBJ41RE4BAFA-AE-E	ELPIDA	获取价格	DDR DRAM Module, 512MX72, 0.3ns, CMOS, ROHS COMPLIANT, DIMM-240
EBJ41RE4BAFA-AG-E	ELPIDA	获取价格	DDR DRAM Module, 512MX72, 0.3ns, CMOS, ROHS COMPLIANT, DIMM-240
EBJ41RE4BAFA-DG-E	ELPIDA	获取价格	DDR DRAM Module, 512MX72, 0.255ns, CMOS, ROHS COMPLIANT, DIMM-240
EBJ41RE4BAFA-DJ-E	ELPIDA	获取价格	DDR DRAM Module, 512MX72, 0.255ns, CMOS, ROHS COMPLIANT, DIMM-240
EBJ41UF8BAS0	ELPIDA	获取价格	4GB DDR3 SDRAM SO-DIMM
EBJ41UF8BAS0-AE-F	ELPIDA	获取价格	4GB DDR3 SDRAM SO-DIMM

与EBJ41HF4B1QA相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

28
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

21
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

50
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

48

产品中心

服务支持

精选活动

关于我们

帮助中心

EBJ41HF4B1QA

EBJ41HF4B1QA 数据手册

与EBJ41HF4B1QA相关器件

与EBJ41HF4B1QA相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

EBJ41HF4B1QA

EBJ41HF4B1QA 数据手册

与EBJ41HF4B1QA相关器件

与EBJ41HF4B1QA相关文章

您还可以找

您在本页遇到什么问题？