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DS90CR285SLC PDF预览

DS90CR285SLC

更新时间： 2024-11-21 19:42:11
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动接口集成电路驱动器
页数 文件大小 规格书
19页 345K
描述
IC QUAD LINE DRIVER, PBGA64, 0.80 MM PITCH, FBGA-64, Line Driver or Receiver

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中文翻译

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DS90CR285SLC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：LFBGA, BGA64,8X8,32Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：7.92差分输出：YES
驱动器位数：4输入特性：STANDARD
接口集成电路类型：LINE DRIVER接口标准：GENERAL PURPOSE
JESD-30 代码：S-PBGA-B64JESD-609代码：e0
长度：8 mm功能数量：4
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA64,8X8,32
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified最大接收延迟：
座面最大高度：1.5 mm子类别：Line Driver or Receivers
最大压摆率：55 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：8 mmBase Number Matches：1

DS90CR285SLC 数据手册

 浏览型号DS90CR285SLC的Datasheet PDF文件第2页浏览型号DS90CR285SLC的Datasheet PDF文件第3页浏览型号DS90CR285SLC的Datasheet PDF文件第4页浏览型号DS90CR285SLC的Datasheet PDF文件第5页浏览型号DS90CR285SLC的Datasheet PDF文件第6页浏览型号DS90CR285SLC的Datasheet PDF文件第7页 
November 2000  
DS90CR285/DS90CR286  
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel  
Link-66 MHz  
General Description  
Features  
n Single +3.3V supply  
The DS90CR285 transmitter converts 28 bits of LVCMOS/  
LVTTL data into four LVDS (Low Voltage Differential Signal-  
ing) data streams. A phase-locked transmit clock is transmit-  
ted in parallel with the data streams over a fifth LVDS link.  
Every cycle of the transmit clock 28 bits of input data are  
sampled and transmitted. The DS90CR286 receiver con-  
verts the LVDS data streams back into 28 bits of LVCMOS/  
LVTTL data. At a transmit clock frequency of 66 MHz, 28 bits  
of TTL data are transmitted at a rate of 462 Mbps per LVDS  
data channel. Using a 66 MHz clock, the data throughput is  
1.848 Gbit/s (231 Mbytes/s).  
<
n Chipset (Tx + Rx) power consumption 250 mW (typ)  
n Power-down mode ( 0.5 mW total)  
<
n Up to 231 Megabytes/sec bandwidth  
n Up to 1.848 Gbps data throughput  
n Narrow bus reduces cable size  
n 290 mV swing LVDS devices for low EMI  
n +1V common mode range (around +1.2V)  
n PLL requires no external components  
n Both devices are offered in a Low profile 56-lead  
TSSOP package  
n DS90CR285SLC is offered in a 64 ball, 0.8mm fine pitch  
ball grid array (FBGA) package for use with the  
DS90CR286ASLC  
n Rising edge data strobe  
n Compatible with TIA/EIA-644 LVDS standard  
The multiplexing of the data lines provides a substantial  
cable reduction. Long distance parallel single-ended buses  
typically require a ground wire per active signal (and have  
very limited noise rejection capability). Thus, for a 28-bit wide  
data and one clock, up to 58 conductors are required. With  
the Channel Link chipset as few as 11 conductors (4 data  
pairs, 1 clock pair and a minimum of one ground) are  
needed. This provides a 80% reduction in required cable  
width, which provides a system cost savings, reduces con-  
nector physical size and cost, and reduces shielding require-  
ments due to the cables’ smaller form factor.  
>
n ESD Rating 7 kV  
n Operating Temperature: −40˚C to +85˚C  
The 28 LVCMOS/LVTTL inputs can support a variety of  
signal combinations. For example, seven 4-bit nibbles or  
three 9-bit (byte + parity) and 1 control.  
Block Diagrams  
DS90CR285  
DS90CR286  
DS012910-1  
DS012910-27  
Order Number DS90CR285MTD or DS90CR285SLC  
See NS Package Number MTD56 or SLC64A  
Order Number DS90CR286MTD  
See NS Package Number MTD56  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2000 National Semiconductor Corporation  
DS012910  
www.national.com  
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与DS90CR285SLC相关器件

型号 品牌 获取价格 描述 数据表
DS90CR285SLCX TI

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 		QUAD LINE DRIVER, PBGA64, 0.80 MM PITCH, FBGA-64
DS90CR286 NSC

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 		+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
DS90CR286A TI

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 		+3.3V 上升沿数据选通 LVDS 28 位 Channel Link 接收器 - 66
DS90CR286A NSC

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 		+3.3V Rising Edge Data Strobe LVDS Receiver 2
DS90CR286A_09 NSC

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 		+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-66 MHz, +3.3V Rising Edge
DS90CR286AMTD NSC

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 		+3.3V Rising Edge Data Strobe LVDS Receiver 2
DS90CR286AMTD TI

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 		+3.3V 上升沿数据选通 LVDS 28 位 Channel Link 接收器 - 66
DS90CR286AMTD/NOPB TI

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 		+3.3V 上升沿数据选通 LVDS 28 位 Channel Link 接收器 - 66
DS90CR286AMTDX ETC

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 		Video Link Interface
DS90CR286AMTDX/NOPB TI

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 		+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link - 66 MHz 56-TSSOP -40 to 8

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