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DS90CR286ASLCX PDF预览

DS90CR286ASLCX

更新时间: 2024-09-14 13:00:43
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
16页 319K
描述
IC QUAD LINE RECEIVER, PBGA64, 0.80 MM PITCH, FBGA-64, Line Driver or Receiver

DS90CR286ASLCX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:LFBGA, BGA64,8X8,32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.55输入特性:DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型:LINE RECEIVER接口标准:EIA-644; TIA-644
JESD-30 代码:S-PBGA-B64JESD-609代码:e0
长度:8 mm功能数量:4
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA64,8X8,32
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified最大接收延迟:
接收器位数:4座面最大高度:1.5 mm
子类别:Line Driver or Receivers最大压摆率:105 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
Base Number Matches:1

DS90CR286ASLCX 数据手册

 浏览型号DS90CR286ASLCX的Datasheet PDF文件第2页浏览型号DS90CR286ASLCX的Datasheet PDF文件第3页浏览型号DS90CR286ASLCX的Datasheet PDF文件第4页浏览型号DS90CR286ASLCX的Datasheet PDF文件第5页浏览型号DS90CR286ASLCX的Datasheet PDF文件第6页浏览型号DS90CR286ASLCX的Datasheet PDF文件第7页 
March 1999  
DS90CR285/DS90CR286  
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel  
Link-66 MHz  
The 28 CMOS/TTL inputs can support a variety of signal  
combinations. For example, seven 4-bit nibbles or three 9-bit  
(byte + parity) and 1 control.  
General Description  
The DS90CR285 transmitter converts 28 bits of CMOS/TTL  
data into four LVDS (Low Voltage Differential Signaling) data  
streams. A phase-locked transmit clock is transmitted in par-  
allel with the data streams over a fifth LVDS link. Every cycle  
of the transmit clock 28 bits of input data are sampled and  
transmitted. The DS90CR286 receiver converts the LVDS  
data streams back into 28 bits of CMOS/TTL data. At a trans-  
mit clock frequency of 66 MHz, 28 bits of TTL data are trans-  
mitted at a rate of 462 Mbps per LVDS data channel. Using  
a 66 MHz clock, the data throughput is 1.848 Gbit/s (231  
Mbytes/s).  
Features  
n Single +3.3V supply  
<
n Chipset (Tx + Rx) power consumption 250 mW (typ)  
<
n Power-down mode ( 0.5 mW total)  
n Up to 231 Megabytes/sec bandwidth  
n Up to 1.848 Gbps data throughput  
n Narrow bus reduces cable size  
n 290 mV swing LVDS devices for low EMI  
n +1V common mode range (around +1.2V)  
n PLL requires no external components  
n Low profile 56-lead TSSOP package  
n Rising edge data strobe  
The multiplexing of the data lines provides a substantial  
cable reduction. Long distance parallel single-ended buses  
typically require a ground wire per active signal (and have  
very limited noise rejection capability). Thus, for a 28-bit wide  
data and one clock, up to 58 conductors are required. With  
the Channel Link chipset as few as 11 conductors (4 data  
pairs, 1 clock pair and a minimum of one ground) are  
needed. This provides a 80% reduction in required cable  
width, which provides a system cost savings, reduces con-  
nector physical size and cost, and reduces shielding require-  
ments due to the cables’ smaller form factor.  
n Compatible with TIA/EIA-644 LVDS standard  
>
n ESD Rating 7 kV  
n Operating Temperature: −40˚C to +85˚C  
Block Diagrams  
DS90CR285  
DS90CR286  
DS012910-1  
DS012910-27  
Order Number DS90CR285MTD  
See NS Package Number MTD56  
Order Number DS90CR286MTD  
See NS Package Number MTD56  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1999 National Semiconductor Corporation  
DS012910  
www.national.com  

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