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DS90CR286A PDF预览

DS90CR286A

更新时间: 2024-09-13 22:40:19
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
12页 253K
描述
+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel LinkΑ66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel LinkΑ66 MHz

DS90CR286A 数据手册

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June 1999  
DS90CR286A/DS90CR216A  
+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit  
Channel Link66 MHz, +3.3V Rising Edge Strobe  
LVDS Receiver 21-Bit Channel Link66 MHz  
General Description  
Features  
n 20 to 66 MHz shift clock support  
The DS90CR286A receiver converts the four LVDS data  
streams (Up to 1.848 Gbps throughput or 231 Megabytes/  
sec bandwidth) back into parallel 28 bits of CMOS/TTL data.  
Also available is the DS90CR216A that converts the three  
LVDS data streams (Up to 1.386 Gbps throughput or 173  
Megabytes/sec bandwidth) back into parallel 21 bits of  
CMOS/TTL data. Both Receivers’ outputs are Rising edge  
strobe.  
%
n 50 duty cycle on receiver output clock  
n Best–in–Class Set & Hold Times on RxOUTPUTs  
n Rx power consumption 270 mW (typ) 66MHz Worst  
Case  
<
@
<
n Rx Power-down mode 200µW (max)  
>
>
n ESD rating 7 kV (HBM), 700V (EIAJ)  
n PLL requires no external components  
This chipset is an ideal means to solve EMI and cable size  
problems associated with wide, high speed TTL interfaces.  
n Compatible with TIA/EIA-644 LVDS standard  
n Low profile 56-lead or 48-lead TSSOP package  
n Operating Temperature: −40˚C to +85˚C  
Block Diagrams  
DS90CR286A  
DS90CR216A  
DS100873-31  
Order Number DS90CR216AMTD  
See NS Package Number MTD48  
DS100873-30  
Order Number DS90CR286AMTD  
See NS Package Number MTD56  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2000 National Semiconductor Corporation  
DS100873  
www.national.com  

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