Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS90CR286A-Q1

DS90CR286A-Q1

更新时间： 2024-11-20 11:07:51

品牌	Logo	应用领域
德州仪器 - TI		驱动线路驱动器或接收器驱动程序和接口
页数	文件大小	规格书
25页	1191K
描述
+3.3V 上升沿数据选通 LVDS 28 位汽车类 Channel Link 接收器 - 66MHz

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DS90CR286A-Q1 数据手册

DS90CR285, DS90CR286

www.ti.com

SNLS130C –MARCH 1999–REVISED MARCH 2013

DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

Check for Samples: DS90CR285, DS90CR286

FEATURES

DESCRIPTION

The DS90CR285 transmitter converts 28 bits of

LVCMOS/LVTTL data into four LVDS (Low Voltage

Differential Signaling) data streams. A phase-locked

transmit clock is transmitted in parallel with the data

streams over a fifth LVDS link. Every cycle of the

transmit clock 28 bits of input data are sampled and

transmitted. The DS90CR286 receiver converts the

LVDS data streams back into 28 bits of

LVCMOS/LVTTL data. At a transmit clock frequency

of 66 MHz, 28 bits of TTL data are transmitted at a

rate of 462 Mbps per LVDS data channel. Using a 66

MHz clock, the data throughput is 1.848 Gbit/s (231

Mbytes/s).

•

Single +3.3V Supply

•

Chipset (Tx + Rx) Power Consumption <250

mW (typ)

•

Power-Down Mode (<0.5 mW total)

Up to 231 Megabytes/sec Bandwidth

Up to 1.848 Gbps Data Throughput

Narrow Bus Reduces Cable Size

290 mV Swing LVDS Devices for Low EMI

+1V Common Mode Range (Around +1.2V)

PLL Requires no External Components

Both Devices are Offered in a Low Profile 56-

Lead TSSOP Package

The multiplexing of the data lines provides

substantial cable reduction. Long distance parallel

single-ended buses typically require a ground wire

per active signal (and have very limited noise

rejection capability). Thus, for a 28-bit wide data and

one clock, up to 58 conductors are required. With the

Channel Link chipset as few as 11 conductors (4 data

pairs, 1 clock pair and a minimum of one ground) are

needed. This provides a 80% reduction in required

cable width, which provides a system cost savings,

reduces connector physical size and cost, and

reduces shielding requirements due to the cables'

smaller form factor.

•

Rising Edge Data Strobe

Compatible with TIA/EIA-644 LVDS Standard

ESD Rating > 7 kV

Operating Temperature: −40°C to +85°C

The 28 LVCMOS/LVTTL inputs can support a variety

of signal combinations. For example, seven 4-bit

nibbles or three 9-bit (byte + parity) and 1 control.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...25

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与DS90CR286A-Q1相关器件

型号	品牌	获取价格	描述	数据表
DS90CR286AQMT	NSC	获取价格	+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-66 MHz, +3.3V Rising Edge
DS90CR286AQMT/NOPB	TI	获取价格	+3.3V 上升沿数据选通 LVDS 28 位汽车类 Channel Link 接收器 -
DS90CR286AQMTX/NOPB	TI	获取价格	+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link - 66 MHz 56-TSSOP -40 to 8
DS90CR286ASLC	NSC	获取价格	IC QUAD LINE RECEIVER, PBGA64, 0.80 MM PITCH, FBGA-64, Line Driver or Receiver
DS90CR286ASLCX	NSC	获取价格	IC QUAD LINE RECEIVER, PBGA64, 0.80 MM PITCH, FBGA-64, Line Driver or Receiver
DS90CR286ASLCX	TI	获取价格	QUAD LINE RECEIVER, PBGA64, 0.80 MM PITCH, FBGA-64
DS90CR286ATDGGQ1	TI	获取价格	3.3V 上升沿数据选通信号 LVDS 接收器 28 位 Channel Link 66M
DS90CR286ATDGGRQ1	TI	获取价格	3.3V 上升沿数据选通信号 LVDS 接收器 28 位 Channel Link 66M
DS90CR286AT-Q1	TI	获取价格	3.3V 上升沿数据选通信号 LVDS 接收器 28 位 Channel Link 66M
DS90CR286MTD	TI	获取价格	DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz

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