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DM74LS273WMX PDF预览

DM74LS273WMX

更新时间: 2024-11-05 23:47:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器
页数 文件大小 规格书
6页 70K
描述
Octal D-Type Flip-Flop

DM74LS273WMX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, MS-013, SOIC-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.21
Is Samacsys:N系列:LS
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:30000000 Hz最大I(ol):0.004 A
位数:8功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):27 mA传播延迟(tpd):24 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:30 MHzBase Number Matches:1

DM74LS273WMX 数据手册

 浏览型号DM74LS273WMX的Datasheet PDF文件第2页浏览型号DM74LS273WMX的Datasheet PDF文件第3页浏览型号DM74LS273WMX的Datasheet PDF文件第4页浏览型号DM74LS273WMX的Datasheet PDF文件第5页浏览型号DM74LS273WMX的Datasheet PDF文件第6页 
October 1988  
Revised March 2000  
DM74LS273  
8-Bit Register with Clear  
General Description  
Features  
The DM74LS273 is a high speed 8-bit register, consisting  
of eight D-type flip-flops with a common Clock and an  
asynchronous active LOW Master Reset. This device is  
supplied in a 20-pin package featuring 0.3 inch row spac-  
ing.  
Edge-triggered  
8-bit high speed register  
Parallel in and out  
Common clock and master reset  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS273WM  
DM74LS273SJ  
DM74LS273N  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
V
= Pin 20  
CC  
GND = Pin 10  
Truth Table  
Pin Descriptions  
Inputs  
CP  
Outputs  
Qn  
Pin Names  
Description  
MR  
Dn  
CP  
Clock Pulse Input (Active Rising Edge)  
Data Inputs  
L
H
H
X
X
H
L
L
H
L
D0–D7  
MR  
Asynchronous Master Reset Input (Active LOW)  
Flip-Flop Outputs  
Q0–Q7  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
© 2000 Fairchild Semiconductor Corporation  
DS009825  
www.fairchildsemi.com  

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