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DM74LS259MX PDF预览

DM74LS259MX

更新时间: 2024-10-31 23:47:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 62K
描述
Addressable D-Type Latch

DM74LS259MX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.42
其他特性:1:8 DMUX FOLLOWED BY LATCH系列:LS
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm逻辑集成电路类型:D LATCH
最大I(ol):0.008 A位数:8
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):36 mA
Prop。Delay @ Nom-Sup:35 ns传播延迟(tpd):35 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:LOW LEVEL宽度:3.9 mm
Base Number Matches:1

DM74LS259MX 数据手册

 浏览型号DM74LS259MX的Datasheet PDF文件第2页浏览型号DM74LS259MX的Datasheet PDF文件第3页浏览型号DM74LS259MX的Datasheet PDF文件第4页浏览型号DM74LS259MX的Datasheet PDF文件第5页浏览型号DM74LS259MX的Datasheet PDF文件第6页 
August 1986  
Revised March 2000  
DM74LS259  
8-Bit Addressable Latches  
General Description  
Features  
These 8-bit addressable latches are designed for general  
purpose storage applications in digital systems. Specific  
uses include working registers, serial-holding registers,  
and active-high decoders or demultiplexers. They are mul-  
tifunctional devices capable of storing single-line data in  
eight addressable latches, and being a 1-of-8 decoder or  
demultiplexer with active-high outputs.  
8-Bit parallel-out storage register performs serial-to-par-  
allel conversion with storage  
Asynchronous parallel clear  
Active high decoder  
Enable/disable input simplifies expansion  
Direct replacement for Fairchild DM9334  
Expandable for N-bit applications  
Four distinct functional modes  
Typical propagation delay times:  
Enable-to-output 18 ns  
Four distinct modes of operation are selectable by control-  
ling the clear and enable inputs as enumerated in the func-  
tion table. In the addressable-latch mode, data at the data-  
in terminal is written into the addressed latch. The  
addressed latch will follow the data input with all unad-  
dressed latches remaining in their previous states. In the  
memory mode, all latches remain in their previous states  
and are unaffected by the data or address inputs. To elimi-  
nate the possibility of entering erroneous data in the  
latches, the enable should be held HIGH (inactive) while  
the address lines are changing. In the 1-of-8 decoding or  
demultiplexing mode, the addressed output will follow the  
level of the D input with all other outputs LOW. In the clear  
mode, all outputs are LOW and unaffected by the address  
and data inputs.  
Data-to-output  
16 ns  
Address-to-output 21 ns  
Clear-to-output  
Fan-out  
17 ns  
8 mA  
IOL (sink current)  
IOH (source current) 0.4 mA  
Typical ICC 22 mA  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS259M  
DM74LS259WM  
DM74LS259N  
M16A  
M16B  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS006418  
www.fairchildsemi.com  

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