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DM74LS26M PDF预览

DM74LS26M

更新时间: 2024-11-05 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器逻辑集成电路光电二极管高压
页数 文件大小 规格书
4页 51K
描述
Quad 2-Input NAND Gate with High Voltage Open-Collector Outputs

DM74LS26M 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.24系列:LS
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm逻辑集成电路类型:NAND GATE
最大I(ol):0.008 A功能数量:4
输入次数:2端子数量:14
最高工作温度:70 °C最低工作温度:
输出特性:OPEN-COLLECTOR封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):4.4 mAProp。Delay @ Nom-Sup:45 ns
传播延迟(tpd):45 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

DM74LS26M 数据手册

 浏览型号DM74LS26M的Datasheet PDF文件第2页浏览型号DM74LS26M的Datasheet PDF文件第3页浏览型号DM74LS26M的Datasheet PDF文件第4页 
August 1986  
Revised March 2000  
DM74LS26  
Quad 2-Input NAND Gate  
with High Voltage Open-Collector Outputs  
General Description  
Pull-Up Resistor Equations  
This device contains four independent gates each of which  
performs the logic NAND function. The open-collector out-  
puts require external pull-up resistors for proper logical  
operation.  
These gates feature high-voltage output ratings (up to 15V)  
for interfacing with 12V systems. Although the outputs are  
rated for 15V, the device supply is still rated for 5V.  
Where:  
N1 (IOH) = total maximum output high current  
for all outputs tied to pull-up resistor  
N2 (IIH) = total maximum input high current for  
all inputs tied to pull-up resistor  
N3 (IIL) = total maximum input low current for  
all inputs tied to pull-up resistor  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS26M  
DM74LS26N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = AB  
Inputs  
Output  
A
L
B
L
Y
H
H
H
L
L
H
L
H
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006358  
www.fairchildsemi.com  

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