Datasheet > DM74LS259N

DM74LS259N

更新时间： 2024-11-04 23:00:43

品牌	Logo	应用领域
美国国家半导体 - NSC		锁存器
页数	文件大小	规格书
6页	156K
描述
8-Bit Addressable Latches

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中文翻译

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数据手册

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DM74LS259N 数据手册

May 1992

DM54LS259/DM74LS259 8-Bit Addressable Latches

General Description

Features

8-Bit parallel-out storage register performs serial-to-par-

allel conversion with storage

Asynchronous parallel clear

Active high decoder

These 8-bit addressable latches are designed for general

purpose storage applications in digital systems. Specific

uses include working registers, serial-holding registers, and

active-high decoders or demultiplexers. They are multifunc-

tional devices capable of storing single-line data in eight

addressable latches, and being a 1-of-8 decoder or demulti-

plexer with active-high outputs.

Enable/disable input simplifies expansion

Direct replacement for Fairchild 9334

Expandable for N-bit applications

Four distinct functional modes

Typical propagation delay times:

Enable-to-output 18 ns

Four distinct modes of operation are selectable by control-

ling the clear and enable inputs as enumerated in the func-

tion table. In the addressable-latch mode, data at the data-

in terminal is written into the addressed latch. The ad-

dressed latch will follow the data input with all unaddressed

latches remaining in their previous states. In the memory

mode, all latches remain in their previous states and are

unaffected by the data or address inputs. To eliminate the

possibility of entering erroneous data in the latches, the en-

able should be held high (inactive) while the address lines

are changing. In the 1-of-8 decoding or demultiplexing

mode, the addressed output will follow the level of the D

input with all other outputs low. In the clear mode, all out-

puts are low and unaffected by the address and data inputs.

Data-to-output 16 ns

Address-to-output 21 ns

Clear-to-output 17 ns

Fan-out

(sink current)

54LS259 4 mA

74LS259 8 mA

(source current) 0.4 mA

Typical I

22 mA

Connection Diagram

Function Table

Inputs

Output of Each

Addressed Other

Dual-In-Line Package

Function

Latch

Output

Clear

Addressable Latch

Memory

8-Line Demultiplexer

Clear

Latch Selection Table

Select Inputs

Latch

Addressed

TL/F/6418–1

Order Number DM54LS259E, DM54LS259J,

DM54LS259W, DM74LS259M,

DM74LS259WM or DM74LS259N

See NS Package Number E20A, J16A,

M16A, M16B, N16E or W16A

Low Level

High Level, L

the Level of the Data Input

0, 1, . . . 7, as Appropriate) before the Indicated

the Level of Q (i

Steady-State Input Conditions Were Established.

1995 National Semiconductor Corporation

TL/F/6418

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

中文翻译

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与DM74LS259N相关器件

型号	品牌	获取价格	描述	数据表
DM74LS259N/A+	ETC	获取价格	Addressable D-Type Latch
DM74LS259N/B+	ETC	获取价格	Addressable D-Type Latch
DM74LS259WM	FAIRCHILD	获取价格	8-Bit Addressable Latches
DM74LS259WM	NSC	获取价格	8-Bit Addressable Latches
DM74LS259WMX	FAIRCHILD	获取价格	Addressable D-Type Latch
DM74LS26	FAIRCHILD	获取价格	Quad 2-Input NAND Gate with High Voltage Open-Collector Outputs
DM74LS260	NSC	获取价格	Dual 5-Input NOR Gate
DM74LS260M	NSC	获取价格	Dual 5-Input NOR Gate
DM74LS260M	TI	获取价格	LS SERIES, DUAL 5-INPUT NOR GATE, PDSO14, 0.150 INCH, PLASTIC, SOIC-14
DM74LS260MX	TI	获取价格	LS SERIES, DUAL 5-INPUT NOR GATE, PDSO14, 0.150 INCH, PLASTIC, SOIC-14

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