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DM74LS265A

更新时间: 2024-11-04 21:54:31
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美国国家半导体 - NSC /
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6页 134K
描述
Hex TRI-STATE Buffers

DM74LS265A 数据手册

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June 1989  
54LS365A/DM54LS365A/DM74LS365A  
Hex TRI-STATE Buffers  
É
General Description  
This device contains six independent gates each of which  
performs a non-inverting buffer function. The outputs have  
the TRI-STATE feature. When enabled, the outputs exhibit  
the low impedance characteristics of a standard LS output  
with additional drive capability to permit the driving of bus  
lines without external resistors. When disabled, both the  
output transistors are turned off presenting a high-imped-  
ance state to the bus line. Thus the output will act neither as  
a significant load nor as a driver. To minimize the possibility  
that two outputs will attempt to take a common bus to oppo-  
site logic levels, the disable time is shorter than the enable  
time of the outputs.  
Features  
Y
Alternate Military/Aerospace device (54LS365A) is  
available. Contact a National Semiconductor Sales Of-  
fice/Distributor for specifications.  
Connection Diagram  
Dual-In-Line Package  
TL/F/6427–1  
Order Number 54LS365ADMQB, 54LS365AFMQB, 54LS365ALMQB,  
DM54LS365AJ, DM54LS365AW, DM74LS265AM or DM74LS365AN  
See NS Package Number E20A, J16A, M16A, N16E or W16A  
Function Table  
e
Y
A
Input  
G2  
Output  
Y
G1  
A
H
X
L
X
H
L
X
X
H
L
Hi-Z  
Hi-Z  
H
L
L
L
e
e
e
H
L
High Logic Level  
Low Logic Level  
X
Either Low or High Logic Level  
e
Hi-Z  
TRI-STATE (Outputs are disabled)  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/6427  
RRD-B30M105/Printed in U. S. A.  

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