DM74LS107A

更新时间： 2024-02-04 22:05:45

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器
页数	文件大小	规格书
6页	122K
描述
Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

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技术参数
数据手册

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DM74LS107A 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP14,.3	Reach Compliance Code：	unknown
风险等级：	5.92	JESD-30 代码：	R-PDIP-T14
JESD-609代码：	e0	逻辑集成电路类型：	J-K FLIP-FLOP
最大频率@ Nom-Sup：	30000000 Hz	最大I（ol）：	0.008 A
功能数量：	2	端子数量：	14
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP14,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	5 V
最大电源电流（ICC）：	8 mA	认证状态：	Not Qualified
子类别：	FF/Latches	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	TTL
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	触发器类型：	MASTER-SLAVE
Base Number Matches：	1

DM74LS107A 数据手册

June 1989

DM54LS107A/DM74LS107A Dual Negative-Edge-

Triggered Master-Slave J-K Flip-Flops with

Clear and Complementary Outputs

General Description

This device contains two independent negative-edge-trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flops on the falling edge of

the clock pulse. The clock triggering occurs at a voltage

level and is not directly related to the transition time of the

negative going edge of the clock pulse. The data on the J

and K inputs may change while the clock is high or low

without affecting the outputs as long as setup and hold

times are not violated. A low logic level on the clear input

will reset the outputs regardless of the logic levels of the

other inputs.

Connection Diagram

Dual-In-Line Package

TL/F/6367–1

Order Number DM54LS107AJ, DM54LS107AW, DM74LS107AM or DM74LS107AN

See NS Package Number J14A, M14A, N14A or W14B

Function Table

Inputs

CLK

Outputs

CLR

Toggle

High Logic Level

Either Low or High Logic Level

Low Logic Level

Negative going edge of pulse.

The output logic level before the indicated input conditions were established.

Toggle

Each output changes to the complement of its previous level on each falling edge of the clock pulse.

1995 National Semiconductor Corporation

TL/F/6367

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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与DM74LS107A相关器件

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DM74LS107AM	NSC	Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Out	获取价格
DM74LS107AN	NSC	Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Out	获取价格
DM74LS107AN/A+	ETC	J-K-Type Flip-Flop	获取价格
DM74LS107AN/B+	ETC	J-K-Type Flip-Flop	获取价格
DM74LS107J	TI	IC,FLIP-FLOP,DUAL,J/K TYPE,LS-TTL,DIP,14PIN,CERAMIC	获取价格
DM74LS107J/A+	ETC	J-K-Type Flip-Flop	获取价格