Datasheet > DM74ALS646_01

DM74ALS646_01

更新时间： 2024-09-15 05:20:27

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
6页	60K
描述
Octal 3-STATE Bus Transceiver and Register

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DM74ALS646_01 数据手册

October 1986

Revised June 2001

DM74ALS646

Octal 3-STATE Bus Transceiver and Register

General Description

Features

This device incorporates an octal bus transceiver and an

octal D-type register configured to enable multiplexed

transmission of data from bus to bus or internal register to

bus.

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V_CCrange

■ Advanced oxide-isolated, ion-implanted Schottky TTL

This bus transceiver features totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-

tively low-impedance loads. The high-impedance state and

increased high-logic level drive provides this device with

the capability of being connected directly to and driving the

bus lines in a bus-organized system without the need for

interface or pull-up components. They are particularly

attractive for implementing buffer registers, I/O ports, bidi-

rectional bus drivers, and working registers.

process

■ 3-STATE buffer outputs drive bus lines directly

■ Multiplexed real-time and stored data

■ Independent registers for A and B buses

The registers in the DM74ALS646 are edge-triggered D-

type flip-flops. On the positive transition of the clock (CAB

or CBA), the input bus data is stored into the appropriate

the A register and the CBA input controls the B register.

The SAB and SBA control pins are provided to select

whether real-time data or stored data is transferred. A LOW

input level selects real-time data, and a HIGH level selects

stored data. The select controls have a “make before

break” configuration to eliminate a glitch which would nor-

mally occur in a typical multiplexer during the transition

between store and real-time data.

The enable G and direction control pins provide four modes

of operation: real-time data transfer from bus A to B, real-

time data transfer from bus B to A, real-time bus A and/or B

data transfer to internal storage, or internally stored data

transfer to bus A or B.

When the enable G pin is LOW, the direction pin selects

which bus receives data. When the enable G pin is HIGH,

both buses become disabled yet their input function is still

enabled.

Ordering Code

Order Number Package Number

Package Description

DM74ALS646WM

DM74ALS646NT

M24B

N24C

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS009172

www.fairchildsemi.com

12 3 4 5 6

中文翻译

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与DM74ALS646_01相关器件

型号	品牌	获取价格	描述	数据表
DM74ALS646-1NT	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS646-1WM	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS646N	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS646N/A+	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS646N/B+	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS646NT	FAIRCHILD	获取价格	Octal 3-STATE Bus Transceiver and Register
DM74ALS646NT/A+	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS646WM	FAIRCHILD	获取价格	Octal 3-STATE Bus Transceiver and Register
DM74ALS646WM/A+	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS646WM/B+	ETC	获取价格	Single 8-bit Bus Transceiver

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