DM74ALS652

更新时间： 2024-09-15 22:56:51

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
6页	61K
描述
Octal 3-STATE Bus Transceiver and Register

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DM74ALS652 数据手册

October 1986

Revised March 2000

DM74ALS652

Octal 3-STATE Bus Transceiver and Register

General Description

This device incorporates an octal transceiver and an octal

D-type register configured to enable transmission of data

from bus to bus or internal register to bus.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V_CCrange

This bus transceiver features totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-

tively low-impedance loads. The high-impedance state and

increased high level logic drive provide this device with the

capability of being connected directly to and driving the bus

lines in a bus organized system without need for interface

or pull-up components. They are particularly attractive for

implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers.

■ Advanced oxide-isolated, ion-implanted Schottky TTL

process

■ 3-STATE buffer-type outputs drive bus lines directly

■ Independent registers and enables for A and B buses

■ Multiplexed real-time and stored data

The registers in the DM74ALS652 are edge-triggered D-

type flip-flops. On the positive transition of the clock (CAB

or CBA), the input data is stored into the appropriate regis-

ter. The CAB input controls the transfer of data into the A

The SAB and SBA control pins are provided to select

whether real-time data or stored data is transferred. A LOW

input level selects real-time data and a HIGH level selects

stored data. The select controls have a “make before

break” configuration to eliminate a glitch which would nor-

mally occur in a typical multiplexer during the transition

between stored and real-time data.

The enable (GAB and GBA) control pins provide four

modes of operation: real-time data transfer from bus A to

B, real-time data transfer from bus B to A, real-time bus A

and/or B data transfer to internal storage, or internal stored

data transfer to bus A and/or B.

Ordering Code:

Order Number

DM74ALS652WM

DM74ALS652NT

Package Number Package Description

M24B

N24C

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

DS009174

www.fairchildsemi.com

12 3 4 5 6

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与DM74ALS652相关器件

型号	品牌	获取价格	描述	数据表
DM74ALS652-01	FAIRCHILD	获取价格	Octal 3-STATE Bus Transceiver and Register
DM74ALS652-1NT	TI	获取价格	ALS SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, SLIM, PLASTIC,
DM74ALS652-1WM	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS652-1WMX	TI	获取价格	ALS SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, 0.300 INCH, PLASTIC, SOIC-2
DM74ALS652M/A+	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS652M/B+	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS652N	TI	获取价格	IC ALS SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDIP24, PLASTIC, DIP-24, Bus Dri
DM74ALS652N/A+	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS652N/B+	ETC	获取价格	Single 8-bit Bus Transceiver
DM74ALS652NT	FAIRCHILD	获取价格	Octal 3-STATE Bus Transceiver and Register

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