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DM74ALS652WM PDF预览

DM74ALS652WM

更新时间： 2024-11-05 22:56:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 61K
描述
Octal 3-STATE Bus Transceiver and Register

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中文翻译

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DM74ALS652WM 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：0.300 INCH, MS-013, SOIC-24
针数：24Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.3
Is Samacsys：N控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ALS
JESD-30 代码：R-PDSO-G24JESD-609代码：e3
长度：15.4 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.048 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：88 mA
Prop。Delay @ Nom-Sup：18 ns传播延迟（tpd）：18 ns
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：7.5 mmBase Number Matches：1

DM74ALS652WM 数据手册

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October 1986  
Revised March 2000  
DM74ALS652  
Octal 3-STATE Bus Transceiver and Register  
General Description  
This device incorporates an octal transceiver and an octal  
D-type register configured to enable transmission of data  
from bus to bus or internal register to bus.  
Features  
■ Switching specifications at 50 pF  
■ Switching specifications guaranteed over full tempera-  
ture and VCC range  
This bus transceiver features totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high level logic drive provide this device with the  
capability of being connected directly to and driving the bus  
lines in a bus organized system without need for interface  
or pull-up components. They are particularly attractive for  
implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
■ Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
■ 3-STATE buffer-type outputs drive bus lines directly  
■ Independent registers and enables for A and B buses  
■ Multiplexed real-time and stored data  
The registers in the DM74ALS652 are edge-triggered D-  
type flip-flops. On the positive transition of the clock (CAB  
or CBA), the input data is stored into the appropriate regis-  
ter. The CAB input controls the transfer of data into the A  
register and the CBA input controls the B register.  
The SAB and SBA control pins are provided to select  
whether real-time data or stored data is transferred. A LOW  
input level selects real-time data and a HIGH level selects  
stored data. The select controls have a “make before  
break” configuration to eliminate a glitch which would nor-  
mally occur in a typical multiplexer during the transition  
between stored and real-time data.  
The enable (GAB and GBA) control pins provide four  
modes of operation: real-time data transfer from bus A to  
B, real-time data transfer from bus B to A, real-time bus A  
and/or B data transfer to internal storage, or internal stored  
data transfer to bus A and/or B.  
Ordering Code:  
Order Number  
DM74ALS652WM  
DM74ALS652NT  
Package Number Package Description  
M24B  
N24C  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS009174  
www.fairchildsemi.com  
123456

中文翻译

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DM74ALS652WM 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALS652A-1DW TI

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 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74ALS652ANT TI

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 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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