Datasheet > 逻辑 > 总线驱动器/收发器> DM74ALS652NT_NL

DM74ALS652NT_NL

更新时间： 2024-11-06 13:07:23

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
6页	61K
描述
Registered Bus Transceiver, ALS Series, 1-Func, 8-Bit, True Output, TTL, PDIP24, 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-24

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DM74ALS652NT_NL 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	24
Reach Compliance Code：	unknown	风险等级：	5.73
系列：	ALS	JESD-30 代码：	R-PDIP-T24
JESD-609代码：	e3	长度：	31.915 mm
逻辑集成电路类型：	REGISTERED BUS TRANSCEIVER	位数：	8
功能数量：	1	端口数量：	2
端子数量：	24	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
输出极性：	TRUE	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	传播延迟（tpd）：	18 ns
认证状态：	Not Qualified	座面最大高度：	5.08 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	TTL	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	7.62 mm	Base Number Matches：	1

DM74ALS652NT_NL 数据手册

October 1986

Revised June 2001

DM74ALS652

Octal 3-STATE Bus Transceiver and Register

General Description

This device incorporates an octal transceiver and an octal

D-type register configured to enable transmission of data

from bus to bus or internal register to bus.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V_CCrange

This bus transceiver features totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-

tively low-impedance loads. The high-impedance state and

increased high level logic drive provide this device with the

capability of being connected directly to and driving the bus

lines in a bus organized system without need for interface

or pull-up components. They are particularly attractive for

implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers.

■ Advanced oxide-isolated, ion-implanted Schottky TTL

process

■ 3-STATE buffer-type outputs drive bus lines directly

■ Independent registers and enables for A and B buses

■ Multiplexed real-time and stored data

The registers in the DM74ALS652 are edge-triggered

D-type flip-flops. On the positive transition of the clock

(CAB or CBA), the input data is stored into the appropriate

the A register and the CBA input controls the B register.

The SAB and SBA control pins are provided to select

whether real-time data or stored data is transferred. A LOW

input level selects real-time data and a HIGH level selects

stored data. The select controls have a “make before

break” configuration to eliminate a glitch which would nor-

mally occur in a typical multiplexer during the transition

between stored and real-time data.

The enable (GAB and GBA) control pins provide four

modes of operation: real-time data transfer from bus A to

B, real-time data transfer from bus B to A, real-time bus A

and/or B data transfer to internal storage, or internal stored

data transfer to bus A and/or B.

Ordering Code:

Order Number Package Number

Package Description

DM74ALS652WM

DM74ALS652NT

M24B

N24C

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

DS009174

www.fairchildsemi.com

12 3 4 5 6

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与DM74ALS652NT_NL相关器件

型号	品牌	获取价格	描述	数据表
DM74ALS652WM	TI	获取价格	ALS SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, 0.300 INCH, PLASTIC, SOIC-2
DM74ALS652WM	FAIRCHILD	获取价格	Octal 3-STATE Bus Transceiver and Register
DM74ALS652WMX	TI	获取价格	ALS SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, 0.300 INCH, PLASTIC, SOP-24
DM74ALS679J/A+	ETC	获取价格	Address Comparator
DM74ALS679N/A+	ETC	获取价格	Address Comparator
DM74ALS679N/B+	ETC	获取价格	Address Comparator
DM74ALS680J/A+	ETC	获取价格	Address Comparator
DM74ALS680N/A+	ETC	获取价格	Address Comparator
DM74ALS680N/B+	ETC	获取价格	Address Comparator
DM74ALS689J/A+	TI	获取价格	IC,IDENTITY COMPARATOR,ALS-TTL,DIP,20PIN,CERAMIC

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