DM2223/2233 Multibank Burst EDO EDRAM
512Kb x 8 Enhanced Dynamic RAM
Product Specification
Enhanced
Memory Systems Inc.
Features
■ On-chip Cache Hit/Miss Comparators Automatically Maintain Cache
Coherency Without External Cache Control
■ Output Latch Enable Allows Extended Data Output (EDO) for
Faster System Operation
■ Hidden Precharge and Refresh Cycles
■ 8Kbit SRAM Cache Memory for 12ns Random Reads Within Four
Active Pages (Multibank Cache)
■ Fast 4Mbit DRAM Array for 30ns Access to Any New Page
■ Write Posting Register for 12ns Random or Burst Writes Within
a Page
■ Write-per-bit Option (DM2233) for Parity and Video Applications
■ Extended 64ms Refresh Period for Low Standby Power
■ Low Profile 300-Mil 44-Pin TSOP-II Package
■ Industrial Temperature Range Option
■ 5ns Output Enable Access Time Allows Fast Interleaving
■ Linear or Interleaved Burst Mode Configurable Without Mode
Register Load Cycles
■ Fast Page to Page Move or Read-Modify-Write Cycles
Description
The Enhanced Memory Systems 4Mb EDRAM combines raw speed
with innovative architecture to offer the optimum cost-performance
solution for high performance local or main memory in computer and
embedded control systems. In most high speed applications, zero-wait-
state operation can be achieved without secondary SRAM cache for
system clock speeds of up to 100MHz without interleaving or 132MHz
with two-way interleaving. The EDRAM outperforms conventional SRAM
cache plus DRAM or synchronous DRAM memory systems by
minimizing wait states on initial reads (hit or miss) and by eliminating
writeback delays. Architectural similarity with JEDEC DRAMs allows a
single memory controller design to support either slow JEDEC DRAMs
or high speed EDRAMs. A system designed in this manner can provide
a simple upgrade path to higher system performance.
■ An optional synchronous burst mode for 100MHz burst transfers
or 132MHz two-way interleaved burst transfers.
■ A controllable output latch provides an extended data (EDO)
mode.
■ Cache size is increased from 2Kbits to 8Kbits. The 8Kbit cache is
organized as four 256 x 8 direct mapped row registers. All row
registers can be accessed without clocking /RE.
■ Concurrent random page write and cache reads from four cache
pages allows fast page-to-page move or read-modify-write cycles.
Architecture
The EDRAM architecture includes an integrated SRAM cache
which operates much like a page mode or static column DRAM.
The EDRAM’s SRAM cache is integrated into the DRAM array as
tightly coupled row registers. The 512K x 8 EDRAM has a total of four
independent DRAM memory banks each with its own 256 x 8 SRAM
row register. Memory reads always occur from the cache row register
The 512K x 8 EDRAM has a control and address interface
compatible with the Enhanced 4M x 1 and 1M x 4 EDRAM products
so that EDRAMs of different organizations can be supported with the
same controller design. The 512K x 8 EDRAM implements the
following additional features which can be supported on new designs: of one of these banks as specified by column address bits A and A
8
9
Pin Configuration
Functional Diagram
/CAL
BE
BM
0-2
Column
Address
Latch
V
V
SS
1
2
3
4
5
6
7
44
43
CC
A -A
W/R
0
9
/F
and Burst
Control
Column Decoder
V
42 /S
SS
DQ
A
41
0
10
4 - 256 X 8 Cache Pages
(Row Registers)
V
A
9
40
39
38
37
36
35
34
33
32
CC
4 - 9 Bit
DQ
A
1
8
Comparators
QLE
/G
DQ
A
2
7
Sense Amps
& Column Write Select
V
A
6
8
SS
DQ
A
3
9
A -A
I/O
Control
and
5
0
10
4 - Last Row
Read Address
Latches
A
QLE
10
11
12
13
14
15
16
17
18
19
20
21
22
4
DQ -DQ
0
7
V
V
CC
SS
Data
Latches
/G
/RE
DQ
4
/S
/CAL
Memory
Array
(2048 X 256 X 8)
Row
Address
Latch
V
V
SS
31
30
29
28
27
26
25
24
23
CC
/WE
DQ
5
A
3
DQ
6
A
2
V
A
1
CC
DQ
7
A
0
V
SS
/WE
BE
V
CC
BM
0
A -A
V
0
9
SS
/F
W/R
/RE
Row Adress
and
Refresh
Control
BM
2
BM
1
Refresh
Counter
V
V
CC
SS
© 1996 Enhanced Memory Systems Inc., 1850 Ramtron Drive, Colorado Springs, CO
Telephone (719) 481-7000, Fax (719) 488-9095
80921
38-2106-001
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.