DAC1627D1G25

更新时间： 2024-11-05 09:58:11

品牌	Logo	应用领域
恩智浦 - NXP		转换器数模转换器
页数	文件大小	规格书
69页	1677K
描述
Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating

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技术参数
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DAC1627D1G25 技术参数

生命周期：	Transferred	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	72
Reach Compliance Code：	unknown	风险等级：	5.69
Is Samacsys：	N	最大模拟输出电压：	3.45 V
转换器类型：	D/A CONVERTER	输入位码：	BINARY, 2'S COMPLEMENT BINARY
输入格式：	PARALLEL, WORD	JESD-30 代码：	S-PQCC-N72
长度：	10 mm	位数：	16
功能数量：	1	端子数量：	72
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
认证状态：	Not Qualified	座面最大高度：	1 mm
标称安定时间 (tstl)：	0.02 µs	标称供电电压：	1.8 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	10 mm
Base Number Matches：	1

DAC1627D1G25 数据手册

DAC1627D1G25

Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and

x8 interpolating

Rev. 1 — 29 April 2011

Objective data sheet

1. General description

The DAC1627D1G25 is a high-speed 16-bit dual channel Digital-to-Analog Converter

(DAC) with selectable ×2, ×4 and ×8 interpolating filters optimized for multi-carrier and

broadband wireless transmitters at sample rates of up to 1.25 Gsps. Supplied from a

3.3 V and a 1.8 V source, the DAC1627D1G25 integrates a differential scalable output

current up to 31.8 mA.

The DAC1627D1G25 is capable of meeting multi-carrier GSM specifications. For

example, with an output frequency of 150 MHz and a DAC clock frequency of 1.22 Gsps

the full-scale dynamic range is:

• SFDR_RBW= 85 dBc (bandwidth = 250 MHz)

• IMD3 = 85 dBc

The Serial Peripheral Interface (SPI) provides full control of the DAC1627D1G25.

The DAC1627D1G25 integrates a Low Voltage Differential Signaling (LVDS) Double Data

Rate (DDR) receiver interface, with an on-chip 100 Ω termination. The LVDS DDR

interface accepts a multiplex input data stream such as interleaved or folded. An internal

LVDS input auto-calibration ensures the robustness and stability of the interface.

Digital on-chip modulation converts the complex I and Q inputs from baseband to IF. The

mixer frequency is set by a 40-bit Numerically Controlled Oscillator (NCO). High resolution

internal gain, phase and offset control provide outstanding image and Local Oscillator

(LO) signal rejection at the system analog modulator output.

An inverse (sin x) / x function ensures a controlled flatness 0.5 dB for high bandwidths at

the DAC output.

Multiple device synchronization allows synchronization of the outputs of multiple DAC

devices. MDS guarantees a maximum skew of one output clock period between several

devices.

The DAC1627D1G25 includes a very low noise capacitor-free integrated Phase-Locked

Loop (PLL) multiplier which generates a DAC clock rate from the LVDS clock rate.

The DAC1627D1G25 is available in a HVQFN72 package (10 mm × 10 mm).

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与DAC1627D1G25相关器件

型号	品牌	获取价格	描述	数据表
DAC1627D1G25HN/C1,	IDT	获取价格	Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating, SOT813-3 Package, Standard M
DAC1628D1G25HN	IDT	获取价格	D/A Converter, 2 Func, PQCC56
DAC1653D1G0NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH
DAC1653D1G5NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH
DAC1653D2G0NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH
DAC1653Q	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1653Q1G0NAGA	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1653Q1G25NAGA	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1653Q1G5NAGA	IDT	获取价格	Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50
DAC1658D1G0NLGA	IDT	获取价格	D/A Converter, 1 Func, Serial Input Loading, 0.02us Settling Time, 8 X 8 MM, 0.85 MM HEIGH

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